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stm8s103k3 stm8s103f3 stm8s103f2 access line, 16 mhz stm8s 8-bit mcu, up to 8 kbytes flash, data eeprom,10-bit adc, 3 timers, uar t , spi, i2c features core ? 16 mhz advanced stm8 core with harvard architecture and 3-stage pipeline ? extended instruction set memories ? program memory: 8 kbytes flash; data retention 20 years at 55 c after 10 kcycles ? data memory: 640 bytes true data eeprom; endurance 300 kcycles ? ram: 1 kbytes clock, reset and supply management ? 2.95 to 5.5 v operating voltage ? flexible clock control, 4 master clock sources: - low power crystal resonator oscillator - external clock input - internal, user-trimmable 16 mhz rc - internal low power 128 khz rc ? clock security system with clock monitor ? power management: - low power modes (wait, active-halt, halt) - switch-of f peripheral clocks individually ? permanently active, low consumption power-on and power-down reset interrupt management ? nested interrupt controller with 32 interrupts ? up to 27 external interrupts on 6 vectors t imers ? advanced control timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead-time insertion and flexible synchronization ? 16-bit general purpose timer , with 3 capcom channels (ic, oc or pwm) ? 8-bit basic timer with 8-bit prescaler ? auto wake-up timer ? 2 watchdog timers: window watchdog and independent watchdog communications interfaces ? uar t with clock output for synchronous operation, smartcard, irda, lin master mode ? spi interface up to 8 mbit/s ? i 2 c interface up to 400 kbit/s analog to digital converter (adc) ? 10-bit, 1 lsb adc with up to 5 multiplexed channels, scan mode and analog watchdog i/os ? up to 28 i/os on a 32-pin package including 21 high sink outputs ? highly robust i/o design, immune against current injection ? development support - embedded single wire interface module (swim) for fast on-chip programming and non intrusive debugging unique id ? 96-bit unique key for each device 1 / 104 docid15441 rev 4 november 2009 www .st.com lqfp32 7x7 ufqfpn32 5x5 tssop20 ufqfpn20 3x3
contents 1 introduction .............................................................................................................. 8 2 description ............................................................................................................... 9 3 block diagram ........................................................................................................ 10 4 product overview ................................................................................................... 11 4.1 central processing unit stm8 ..................................................................................... 11 4.2 single wire interface module (swim) and debug module (dm) .................................. 11 4.3 interrupt controller ....................................................................................................... 12 4.4 flash program and data eeprom memory ................................................................ 12 4.5 clock controller ............................................................................................................ 13 4.6 power management .................................................................................................... 14 4.7 w atchdog timers .......................................................................................................... 14 4.8 auto wakeup counter ................................................................................................... 15 4.9 beeper ......................................................................................................................... 15 4.10 tim1 - 16-bit advanced control timer ......................................................................... 15 4.1 1 tim2 - 16-bit general purpose timer .......................................................................... 16 4.12 tim4 - 8-bit basic timer .............................................................................................. 16 4.13 analog-to-digital converter (adc1) ............................................................................ 16 4.14 communication interfaces ......................................................................................... 17 4.14.1 uar t1 ............................................................................................... 17 4.14.2 spi ..................................................................................................... 18 4.14.3 i2c ...................................................................................................... 18 5 pinout and pin description ................................................................................... 19 5.1 stm8s103k ufqfpn32/lqfp32 pinout and description .......................................... 20 5.2 stm8s103f tssop20 pinout .................................................................................... 22 5.3 stm8s103f ufqfpn20 pinout .................................................................................. 23 5.4 stm8s103f tssop20/ufqfpn20 pin description ................................................... 23 5.5 alternate function remapping ....................................................................................... 25 6 memory and register map ..................................................................................... 26 6.1 memory map ................................................................................................................ 26 6.2 register map ............................................................................................................... 27 6.2.1 i/o port hardware register map ............................................................ 27 6.2.2 general hardware register map .......................................................... 28 6.2.3 cpu/swim/debug module/interrupt controller registers ..................... 35 7 interrupt vector mapping ...................................................................................... 37 8 option bytes ........................................................................................................... 39 8.1 alternate function remapping bits ................................................................................ 41 9 unique id ................................................................................................................ 44 docid15441 rev 4 2 / 104 stm8s103k3 stm8s103f3 stm8s103f2 contents
10 electrical characteristics .................................................................................... 45 10.1 parameter conditions ................................................................................................. 45 10.1.1 minimum and maximum values ......................................................... 45 10.1.2 t ypical values ..................................................................................... 45 10.1.3 t ypical curves .................................................................................... 45 10.1.4 loading capacitor ............................................................................... 45 10.1.5 pin input voltage ................................................................................. 46 10.2 absolute maximum ratings ........................................................................................ 46 10.3 operating conditions .................................................................................................. 47 10.3.1 vcap external capacitor .................................................................... 49 10.3.2 supply current characteristics ............................................................ 50 10.3.3 external clock sources and timing characteristics ............................. 59 10.3.4 internal clock sources and timing characteristics ............................... 61 10.3.5 memory characteristics ...................................................................... 64 10.3.6 i/o port pin characteristics ................................................................. 65 10.3.7 reset pin characteristics .................................................................... 73 10.3.8 spi serial peripheral interface ............................................................ 75 10.3.9 i 2 c interface characteristics ............................................................... 78 10.3.10 10-bit adc characteristics ................................................................ 79 10.3.1 1 emc characteristics ......................................................................... 82 1 1 package characteristics ...................................................................................... 86 1 1.1 ecopack packages .................................................................................................... 86 1 1.2 package mechanical data .......................................................................................... 86 1 1.2.1 32- pin lqfp package mechanical data ............................................ 86 1 1.2.2 32-lead ufqfpn package mechanical data ...................................... 87 1 1.2.3 20-lead ufqfpn package mechanical data ...................................... 88 1 1.2.4 ufqfpn recommended footprint ....................................................... 90 1 1.2.5 20-pin tssop package mechanical data .......................................... 91 1 1.3 thermal characteristics .............................................................................................. 92 1 1.3.1 reference document .......................................................................... 93 1 1.3.2 selecting the product temperature range ........................................... 93 12 ordering information ........................................................................................... 94 12.1 stm8s103 f astrom microcontroller option list ..................................................... 95 13 stm8 development tools .................................................................................. 100 13.1 emulation and in-circuit debugging tools ................................................................. 100 13.2 software tools .......................................................................................................... 100 13.2.1 stm8 toolset .................................................................................... 101 13.2.2 c and assembly toolchains .............................................................. 101 13.3 programming tools .................................................................................................. 101 14 revision history ................................................................................................. 102 3 / 104 docid15441 rev 4 contents stm8s103k3 stm8s103f3 stm8s103f2
list of tables t able 1. stm8s103xx access line features ............................................................................................. 9 t able 2. peripheral clock gating bit assignments in clk_pckenr1/2 registers .................................. 14 t able 3. tim timer features .................................................................................................................... 16 t able 4. legend/abbreviations .............................................................................................................. 19 t able 5. ufqfpn32/lqfp32 pin description ........................................................................................ 20 t able 6. stm8s103f pin description ..................................................................................................... 23 t able 7. i/o port hardware register map ................................................................................................ 27 t able 8. general hardware register map ............................................................................................... 28 t able 9. cpu/swim/debug module/interrupt controller registers ......................................................... 35 t able 10. interrupt mapping ................................................................................................................... 37 t able 1 1. option bytes ......................................................................................................................... 102 t able 12. option byte description ........................................................................................................... 39 t able 13. stm8s103k alternate function remapping bits for 32-pin devices ........................................ 41 t able 14. stm8s103f alternate function remapping bits for 20-pin devices ........................................ 42 t able 15. unique id registers (96 bits) ................................................................................................. 102 t able 16. v oltage characteristics ........................................................................................................... 46 t able 17. current characteristics ........................................................................................................... 47 t able 18. thermal characteristics .......................................................................................................... 47 t able 19. general operating conditions ................................................................................................. 47 t able 20. operating conditions at power-up/power-down ...................................................................... 49 t able 21. t otal current consumption with code execution in run mode at v dd = 5 v ............................. 50 t able 22. t otal current consumption with code execution in run mode at v dd = 3.3 v .......................... 51 t able 23. t otal current consumption in wait mode at v dd = 5 v ............................................................ 52 t able 24. t otal current consumption in wait mode at v dd = 3.3 v ......................................................... 52 t able 25. t otal current consumption in active halt mode at v dd = 5 v .................................................. 53 t able 26. t otal current consumption in active halt mode at v dd = 3.3 v ............................................... 53 t able 27. t otal current consumption in halt mode at v dd = 5 v ............................................................. 54 t able 28. t otal current consumption in halt mode at v dd = 3.3 v .......................................................... 54 t able 29. w akeup times ......................................................................................................................... 55 t able 30. t otal current consumption and timing in forced reset state .................................................... 56 t able 31. peripheral current consumption ............................................................................................. 56 t able 32. hse user external clock characteristics ................................................................................. 59 t able 33. hse oscillator characteristics ................................................................................................. 60 t able 34. hsi oscillator characteristics .................................................................................................. 61 t able 35. lsi oscillator characteristics ................................................................................................... 63 t able 36. ram and hardware registers .................................................................................................. 64 t able 37. flash program memory/data eeprom memory .................................................................... 64 t able 38. i/o static characteristics ......................................................................................................... 65 t able 39. output driving current (standard ports) .................................................................................. 67 t able 40. output driving current (true open drain ports) ........................................................................ 67 t able 41. output driving current (high sink ports) .................................................................................. 67 t able 42. nrst pin characteristics ........................................................................................................ 73 t able 43. spi characteristics .................................................................................................................. 76 t able 44. i 2 c characteristics .................................................................................................................. 78 t able 45. adc characteristics ................................................................................................................ 79 t able 46. adc accuracy with r ain < 10 k , v dd = 5 v ......................................................................... 80 t able 47. adc accuracy with r ain < 10 k r ain , v dd = 3.3 v .............................................................. 80 docid15441 rev 4 4 / 104 stm8s103k3 stm8s103f3 stm8s103f2 list of tables
t able 48. ems data ................................................................................................................................ 83 t able 49. emi data ................................................................................................................................. 83 t able 50. esd absolute maximum ratings ............................................................................................. 84 t able 51. electrical sensitivities ............................................................................................................. 84 t able 52. 32-pin low profile quad flat package mechanical data ............................................................ 86 t able 53. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data ............................. 88 t able 54. 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data .... 89 t able 55. 20-pin, 4.40 mm body , 0.65 mm pitch mechanical data ......................................................... 92 t able 56. thermal characteristics .......................................................................................................... 93 t able 57. document revision history .................................................................................................... 102 5 / 104 docid15441 rev 4 list of tables stm8s103k3 stm8s103f3 stm8s103f2
list of figures figure 1. block diagram ......................................................................................................................... 10 figure 2. flash memory organisation .................................................................................................... 13 figure 3. stm8s103k ufqfpn32/lqfp32 pinout .............................................................................. 20 figure 4. stm8s103f tssop20-pin pinout .......................................................................................... 22 figure 5. stm8s103f ufqfpn20-pin pinout ....................................................................................... 23 figure 6. memory map ........................................................................................................................... 26 figure 7. pin loading conditions ............................................................................................................. 45 figure 8. pin input voltage ..................................................................................................................... 46 figure 9. f cpumax versus v dd ................................................................................................................ 49 figure 10. external capacitor c ext ....................................................................................................... 50 figure 1 1. t yp i dd(run) vs. v dd hse user external clock, f cpu = 16 mhz ............................................. 57 figure 12. t yp i dd(run) vs. f cpu hse user external clock, v dd = 5 v .................................................... 57 figure 13. t yp i dd(run) vs. v dd hsi rc osc, f cpu = 16 mhz ................................................................. 58 figure 14. t yp i dd(wfi) vs. v dd hse user external clock, f cpu = 16 mhz .............................................. 58 figure 15. t yp i dd(wfi) vs. f cpu hse user external clock, v dd = 5 v ..................................................... 59 figure 16. t yp i dd(wfi) vs. v dd hsi rc osc, f cpu = 16 mhz ................................................................. 59 figure 17. hse external clocksource ..................................................................................................... 60 figure 18. hse oscillator circuit diagram ............................................................................................... 61 figure 19. t ypical hsi accuracy at v dd = 5 v vs 5 temperatures .......................................................... 62 figure 20. t ypical hsi frequency variation vs v dd @ 4 temperatures .................................................. 63 figure 21. t ypical lsi frequency variation vs v dd @ 4 temperatures ................................................... 63 figure 22. t ypical v il and v ih vs v dd @ 4 temperatures ...................................................................... 66 figure 23. t ypical pull-up resistance vs v dd @ 4 temperatures ............................................................ 66 figure 24. t ypical pull-up current vs v dd @ 4 temperatures ................................................................. 67 figure 25. t yp. v ol @ v dd = 5 v (standard ports) ................................................................................ 68 figure 26. t yp. v ol @ v dd = 3.3 v (standard ports) ............................................................................. 69 figure 27. t yp. v ol @ v dd = 5 v (true open drain ports) ...................................................................... 69 figure 28. t yp. v ol @ v dd = 3.3 v (true open drain ports) ................................................................... 70 figure 29. t yp. v ol @ v dd = 5 v (high sink ports) ................................................................................ 70 figure 30. t yp. v ol @ v dd = 3.3 v (high sink ports) ............................................................................. 71 figure 31. t yp. v dd - v oh @ v dd = 5 v (standard ports) ....................................................................... 71 figure 32. t yp. v dd - v oh @ v dd = 3.3 v (standard ports) ................................................................... 72 figure 33. t yp. v dd - v oh @ v dd = 5 v (high sink ports) ....................................................................... 72 figure 34. t yp. v dd - v oh @ v dd = 3.3 v (high sink ports) .................................................................... 73 figure 35. t ypical nrst v il and v ih vs v dd @ 4 temperatures ........................................................... 74 figure 36. t ypical nrst pull-up resistance vs v dd @ 4 temperatures ................................................. 74 figure 37. t ypical nrst pull-up current vs v dd @ 4 temperatures ...................................................... 75 figure 38. recommended reset pin protection ...................................................................................... 75 figure 39. spi timing diagram - slave mode and cpha = 0 .................................................................. 77 figure 40. spi timing diagram - slave mode and cpha = 1 .................................................................. 77 figure 41. spi timing diagram - master mode (1) ................................................................................... 78 figure 42. adc accuracy characteristics ............................................................................................... 81 figure 43. t ypical application with adc ................................................................................................ 82 figure 44. 32-pin low profile quad flat package (7 x 7) .......................................................................... 86 figure 45. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................ 87 figure 46. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................ 88 figure 47. recommended footprint for on-board emulation .................................................................. 90 docid15441 rev 4 6 / 104 stm8s103k3 stm8s103f3 stm8s103f2 list of figures
figure 48. recommended footprint without on-board emulation ........................................................... 91 figure 49. 20-pin, 4.40 mm body , 0.65 mm pitch ................................................................................... 91 figure 50. stm8s103x access line ordering information scheme ......................................................... 94 7 / 104 docid15441 rev 4 list of figures stm8s103k3 stm8s103f3 stm8s103f2
introduction 1 this datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. ? for complete information on the stm8s microcontroller memory , registers and peripherals, please refer to the stm8s microcontroller family reference manual (rm0016). ? for information on programming, erasing and protection of the internal flash memory please refer to the stm8s flash programming manual (pm0051). ? for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). ? for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044). docid15441 rev 4 8 / 104 stm8s103k3 stm8s103f3 stm8s103f2 introduction
description 2 the stm8s103x access line 8-bit microcontrollers of fer 8 kbytes flash program memory , plus integrated true data eeprom. the stm8s microcontroller family reference manual (rm0016) refers to devices in this family as low-density . they provide the following benefits: ? reduced system cost - integrated true data eeprom for up to 300 k write/erase cycles - high system integration level with internal clock oscillators, watchdog and brown-out reset. ? performance and robustness - 16 mhz cpu clock frequency - robust i/o, independent watchdogs with separate clock source - clock security system ? full documentation and a wide choice of development tools ? advanced core and peripherals made in a state-of-the art technology t able 1: stm8s103xx access line features stm8s103f2 stm8s103f3 stm8s103k3 device 20 20 32 pin count 16 16 28 no. of maximum gpio (i/o) 16 16 27 ext. interrupt pins 7 7 7 t imer capcom channels 2 2 3 t imer complem. outputs 5 5 4 a/d converter channels 12 12 21 high sink i/os 4k 8k 8k low density flash program memory (bytes) 640 (1) 640 (1) 640 (1) data eeprom (bytes) 1k 1k 1k ram (bytes) multipurpose timer (tim1), spi, i 2 c, uar t window wdg,independent wdg, adcpwm timer (tim2), 8-bit timer (tim4) peripheral set (1) no read-while-write (r ww) capability 9 / 104 docid15441 rev 4 description stm8s103k3 stm8s103f3 stm8s103f2
block diagram 3 figure 1: block diagram docid15441 rev 4 10 / 104 stm8s103k3 stm8s103f3 stm8s103f2 block diagram xt al 1-16 mhz rc int. 16 mhz rc int. 128 khz stm8 core deb ug/swim spi u ar t1 16-bit gener al pur pose a wu timer reset b loc k reset por bor cloc k controller detector cloc k to per ipher als and core 8 mbit/s lin master address and data b us windo w wdg 8 kb ytes 640 b ytes 1 kb yte adc1 4 capcom reset 400 kbit/s single wire deb ug interf . spi em ul. channels +3 prog r am flash 16-bit adv anced control timer (tim1) 8-bit basic timer data eepr om ram up to beeper 1/2/4 khz beep independent wdg (tim4) 3 capcom channels up to complementar y outputs timer (tim2) up to 5 channels i 2 c
product overview 4 the following section intends to give an overview of the basic features of the device functional modules and peripherals. for more detailed information please refer to the corresponding family reference manual (rm0016). central processing unit stm8 4.1 the 8-bit stm8 core is designed for code ef ficiency and performance. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. architecture and registers ? harvard architecture ? 3-stage pipeline ? 32-bit wide program memory bus - single cycle fetching for most instructions ? x and y 16-bit index registers - enabling indexed addressing modes with or without of fset and read-modify-write type data manipulations ? 8-bit accumulator ? 24-bit program counter - 16-mbyte linear memory space ? 16-bit stack pointer - access to a 64 k-level stack ? 8-bit condition code register - 7 condition flags for the result of the last instruction addressing ? 20 addressing modes ? indexed indirect addressing mode for look-up tables located anywhere in the address space ? stack pointer relative addressing mode for local variables and parameter passing instruction set ? 80 instructions with 2-byte average instruction size ? standard data movement and logic/arithmetic functions ? 8-bit by 8-bit multiplication ? 16-bit by 8-bit and 16-bit by 16-bit division ? bit manipulation ? data transfer between stack and accumulator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory-to-memory transfers single wire interface module (swim) and debug module (dm) 4.2 the single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming. 1 1 / 104 docid15441 rev 4 product overview stm8s103k3 stm8s103f3 stm8s103f2
swim single wire interface module for direct access to the debug module and memory programming. the interface can be activated in all device operation modes. the maximum data transmission speed is 145 bytes/ms. debug module the non-intrusive debugging module features a performance close to a full-featured emulator . beside memory and peripherals, also cpu operation can be monitored in real-time by means of shadow registers. ? r/w to ram and peripheral registers in real-time ? r/w access to all resources by stalling the cpu ? breakpoints on all program-memory instructions (software breakpoints) ? t wo advanced breakpoints, 23 predefined configurations interrupt controller 4.3 ? nested interrupts with three software priority levels ? 32 interrupt vectors with hardware priority ? up to 27 external interrupts on 6 vectors including tli ? t rap and reset interrupts flash program and data eeprom memory 4.4 ? 8 kbytes of flash program single voltage flash memory ? 640 bytes true data eeprom ? user option byte area w rite protection (wp) w rite protection of flash program memory and data eeprom is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. there are two levels of write protection. the first level is known as mass (memory access security system). mass is always enabled and protects the main flash program memory , data eeprom and option bytes. t o perform in-application programming (iap), this write protection can be removed by writing a mass key sequence in a control register . this allows the application to write to data eeprom, modify the contents of main program memory or the device option bytes. a second level of write protection, can be enabled to further protect a specific area of memory known as ubc (user boot code). refer to the figure below . the size of the ubc is programmable through the ubc option byte, in increments of 1 page (64-byte block) by programming the ubc option byte in icp mode. this divides the program memory into two areas: ? main program memory: up to 8 kbytes minus ubc ? user-specific boot code (ubc): configurable up to 8 kbytes the ubc area remains write-protected during in-application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot docid15441 rev 4 12 / 104 stm8s103k3 stm8s103f3 stm8s103f2 product overview
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the iap and communication routines. figure 2: flash memory organisation read-out protection (rop) the read-out protection blocks reading and writing the flash program memory and data eeprom memory in icp mode (and debug mode). once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory . even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller . clock controller 4.5 the clock controller distributes the system clock (f master ) coming from dif ferent oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features ? clock prescaler: t o get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler . ? safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register . the clock signal is not switched until the new clock source is ready . the design guarantees glitch-free switching. ? clock management: t o reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory . ? master clock sources: four dif ferent clock sources can be used to drive the master clock: - 1-16 mhz high-speed external crystal (hse) - up to 16 mhz high-speed user-external clock (hse user-ext) - 16 mhz high-speed internal rc oscillator (hsi) - 128 khz low-speed internal rc (lsi) 13 / 104 docid15441 rev 4 product overview stm8s103k3 stm8s103f3 stm8s103f2 ubc area prog r am memor y area data memor y area ( 640 b ytes) remains wr ite protected dur ing iap data eepr om memor y wr ite access possib le f or iap option b ytes prog r ammab le b ytes (1 page) up to 8 kb ytes (in 1 page steps) area from 64 ? lo w density flash prog r am memor y (8 kb ytes)
? startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mhz/8) is automatically selected by the css and an interrupt can optionally be generated. ? configurable main clock output (cco): this outputs an external clock for use by the application. t able 2: peripheral clock gating bit assignments in clk_pckenr1/2 registers peripheral clock bit peripheral clock bit peripheral clock bit peripheral clock bit adc pcken23 reserved pcken27 uar t1 pcken13 tim1 pcken17 a wu pcken22 reserved pcken26 reserved pcken12 reserved pcken16 reserved pcken21 reserved pcken25 spi pcken1 1 tim2 pcken15 reserved pcken20 reserved pcken24 i 2 c pcken10 tim4 pcken14 power management 4.6 for ef ficent power management, the application can be put in one of four dif ferent low-power modes. y ou can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. ? w ait mode: in this mode, the cpu is stopped, but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. ? active halt mode with regulator on: in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto wake up unit (a wu). the main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator of f, but the wakeup time is faster . w akeup is triggered by the internal a wu interrupt, external interrupt or reset. ? active halt mode with regulator of f: this mode is the same as active halt with regulator on, except that the main voltage regulator is powered of f, so the wake up time is slower . ? halt mode: in this mode the microcontroller uses the least power . the cpu and peripheral clocks are stopped, the main voltage regulator is powered of f. w akeup is triggered by external event or reset. w atchdog timers 4.7 the watchdog system is based on two independent timers providing maximum security to the applications. activation of the watchdog timers is controlled by option bytes or by software. once activated, the watchdogs cannot be disabled by the user program without performing a reset. docid15441 rev 4 14 / 104 stm8s103k3 stm8s103f3 stm8s103f2 product overview
w indow watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly . the application software must refresh the counter before time-out and during a limited time window . a reset is generated in two situations: 1. t imeout: at 16 mhz cpu clock the time-out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the downcounter is refreshed before its value is lower than the one stored in the window register . independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure the iwdg time base spans from 60 s to 1 s. auto wakeup counter 4.8 ? used for auto wakeup from active halt mode ? clock source: internal 128 khz internal low frequency rc oscillator or external clock ? lsi clock can be internally connected to tim1 input capture channel 1 for calibration beeper 4.9 the beeper function outputs a signal on the beep pin for sound generation. the signal is in the range of 1, 2 or 4 khz. tim1 - 16-bit advanced control timer 4.10 this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-time control and center-aligned pwm capability , the field of applications is extended to motor control, lighting and half-bridge driver ? 16-bit up, down and up/down autoreload counter with 16-bit prescaler ? four independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output ? synchronization module to control the timer with external signals ? break input to force the timer outputs into a defined state ? three complementary outputs with adjustable dead time ? encoder mode 15 / 104 docid15441 rev 4 product overview stm8s103k3 stm8s103f3 stm8s103f2
? interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break tim2 - 16-bit general purpose timer 4.1 1 ? 16-bit autoreload (ar) up-counter ? 15-bit prescaler adjustable to fixed power of 2 ratios 132768 ? 3 individually configurable capture/compare channels ? pwm mode ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update tim4 - 8-bit basic timer 4.12 ? 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 ? clock source: cpu clock ? interrupt source: 1 x overflow/update t able 3: tim timer features t imer synchronization/ chaining ext. trigger complem. outputs capcom channels counting mode prescaler counter size (bits) t imer no y es 3 4 up/down any integer from 1 to 65536 16 tim1 no 0 3 up any power of 2 from 1 to 32768 16 tim2 no 0 0 up any power of 2 from 1 to 128 8 tim4 analog-to-digital converter (adc1) 4.13 the stm8 family products contain a 10-bit successive approximation a/d converter (adc1) with up to 5 external multiplexed input channels and the following main features: ? input voltage range: 0 to v dd ? conversion time: 14 clock cycles ? single and continuous and buf fered continuous conversion modes ? buf fer size (n x 10 bits) where x = number of input channels ? scan mode for single and continuous conversion of a sequence of channels ? analog watchdog capability with programmable upper and lower thresholds ? analog watchdog interrupt ? external trigger input docid15441 rev 4 16 / 104 stm8s103k3 stm8s103f3 stm8s103f2 product overview
? t rigger from tim1 trgo ? end of conversion (eoc) interrupt communication interfaces 4.14 the following communication interfaces are implemented: ? uar t1: full feature uar t , synchronous mode, spi master mode, smartcard mode, irda mode, single wire mode, lin2.1 master capability ? spi : full and half-duplex, 8 mbit/s ? i2c: up to 400 kbit/s uart1 4.14.1 main features ? one mbit/s full duplex sci ? spi emulation ? high precision baud rate generator ? smartcard emulation ? irda sir encoder decoder ? lin master mode ? single wire half duplex mode asynchronous communication (uart mode) ? full duplex communication - nrz standard format (mark/space) ? programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency ? separate enable bits for transmitter and receiver ? t wo receiver wakeup modes: - address bit (msb) - idle line (interrupt) ? t ransmission error detection with interrupt generation ? parity control synchronous communication ? full duplex synchronous transfers ? spi master operation ? 8-bit data communication ? maximum speed: 1 mbit/s at 16 mhz (f cpu /16) lin master mode ? emission: generates 13-bit synch break frame ? reception: detects 1 1-bit break frame 17 / 104 docid15441 rev 4 product overview stm8s103k3 stm8s103f3 stm8s103f2
spi 4.14.2 ? maximum speed: 8 mbit/s (f master /2) both for master and slave ? full duplex synchronous transfers ? simplex synchronous transfers on two lines with a possible bidirectional data line ? master or slave operation - selectable by hardware or software ? crc calculation ? 1 byte tx and rx buf fer ? slave/master selection input pin i2c 4.14.3 ? i2c master features: - clock generation - start and stop generation ? i2c slave features: - programmable i2c address detection - stop bit detection ? generation and detection of 7-bit/10-bit addressing and general call ? supports dif ferent communication speeds: - standard speed (up to 100 khz) - fast speed (up to 400 khz) docid15441 rev 4 18 / 104 stm8s103k3 stm8s103f3 stm8s103f2 product overview
pinout and pin description 5 t able 4: legend/abbreviations i= input, o = output, s = power supply t ype cm = cmos input level hs = high sink output o1 = slow (up to 2 mhz) output speed o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset float = floating, wpu = weak pull-up input port and control configuration t = t rue open drain, od = open drain, pp = push pull output bold x reset state high sink capability (hs) t rue open drain (p-buf fer and protection diode to v dd not implemented) (t) alternate function remapping option [ ] 19 / 104 docid15441 rev 4 pinout and pin description stm8s103k3 stm8s103f3 stm8s103f2
stm8s103k ufqfpn32/lqfp32 pinout and description 5.1 figure 3: stm8s103k ufqfpn32/lqfp32 pinout t able 5: ufqfpn32/lqfp32 pin description alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin no. pp od speed high sink (1) ext. interrupt wpu floating reset x i/o nrst 1 resonator/ crystal in port a1 x x o1 x x x i/o p a1/ osci (2) 2 resonator/ crystal out port a2 x x o1 x x x i/o p a2/ oscout 3 digital ground s v ss 4 1.8 v regulator capacitor s vcap 5 digital power supply s v dd 6 spi master/ slave select [afr1] t imer 2 channel 3 port a3 x x o3 hs x x x i/o p a3/ im2_ch3 [spi_nss] 7 port f4 x x o1 x x i/o pf4 8 port b7 x x o1 x x x i/o pb7 9 docid15441 rev 4 20 / 104 stm8s103k3 stm8s103f3 stm8s103f2 pinout and pin description i 2 c_scl/(t) pb4 tim1_etr/ain3/(hs) pb3 tim1_ch3n/ ain2/ (hs) pb2 tim1_ch2n/ ain1/(hs) pb1 tim1_ch1n/ain0/(hs) pb0 pb7 pb6 i 2 c_sd a/ (t) pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 vcap v dd [spi_nss] tim2_ch3/(hs)p a3 pf4 nrst oscin/p a1 oscout/p a2 v ss pc3 (hs) /tim1_ch3 pc2 (hs) /tim1_ch2 pc1 (hs) /tim1_ch1/ u ar t1_ck pe5 (hs) /spi_nss pc7 (hs)/spi_miso pc6 (hs)/spi_mosi pc5 (hs)/spi_sck pc4 (hs) /tim1_ch4/clk_cco pd3 (hs)/tim2_ch2/adc_etr pd2 (hs) [tim2_ch3] pd1 (hs)/swim pd0 (hs)/ tim1_bkin [clk_cco] pd7 (hs)/tli ( tim1_ch4) pd6 (hs)/u ar t1_rx pd5 (hs)/u ar t1_tx pd4 (hs)/beep/tim2_ch1
alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin no. pp od speed high sink (1) ext. interrupt wpu floating port b6 x x o1 x x x i/o pb6 10 i 2 c data port b5 t (3) o1 x x i/o pb5/ i 2 c_sda 1 1 i 2 c clock port b4 t (3) o1 x x i/o pb4/ i 2 c_scl 12 analog input 3/ t imer 1 external trigger port b3 x x o3 hs x x x i/o pb3/ain3/ tim1_etr 13 analog input 2/ t imer 1 - port b2 x x o3 hs x x x i/o pb2/ain2/ tim1_ch3n 14 inverted channel 3 analog input 1/ t imer 1 - port b1 x x o3 hs x x x i/o pb1/ain1/ tim1_ch2n 15 inverted channel 2 analog input 0/ t imer 1 - port b0 x x o3 hs x x x i/o pb0/ain0/ tim1_ch1n 16 inverted channel 1 spi master/slave select port e5 x x o3 hs x x x i/o pe5/spi_nss 17 t imer 1 - channel 1 uar t1 clock port c1 x x o3 hs x x x i/o pc1/ im1_ch1/ uar t1_ck 18 t imer 1 - channel 2 port c2 x x o3 hs x x x i/o pc2/ tim1_ch2 19 t imer 1 - channel 3 port c3 x x o3 hs x x x i/o pc3/ im1_ch3 20 t imer 1 - channel 4 port c4 x x o3 hs x x x i/o pc4/ im1_ch4/ clk_cco 21 /configurable clock output spi clock port c5 x x o3 hs x x x i/o pc5/ spi_sck 22 spi master out/slave in port c6 x x o3 hs x x x i/o pc6/ pi_mosi 23 spi master in/ slave out port c7 x x o3 hs x x x i/o pc7/ pi_miso 24 configurable clock output [afr5] t imer 1 - break input port d0 x x o3 hs x x x i/o pd0/ im1_bkin [clk_cco] 25 swim data interface port d1 x x o4 hs x x x i/o pd1/ swim 26 21 / 104 docid15441 rev 4 pinout and pin description stm8s103k3 stm8s103f3 stm8s103f2
alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin no. pp od speed high sink (1) ext. interrupt wpu floating t imer 2 - channel 3[afr1] port d2 x x o3 hs x x x i/o pd2 [tim2_ch3] 27 t imer 2 - channel 2/adc external trigger port d3 x x o3 hs x x x i/o pd3/ tim2_ch2/ adc_etr 28 t imer 2 - channel 1/beep output port d4 x x o3 hs x x x i/o pd4/beep/ tim2_ch1 29 uar t1 data transmit port d5 x x o3 hs x x x i/o pd5/ uar t1_tx 30 uar t1 data receive port d6 x x o3 hs x x x i/o pd6/ uar t1_rx 31 t imer 1 - channel 4 [afr6] t op level interrupt port d7 x x o3 hs x x x i/o pd7/ tli [tim1_ch4] 32 (1) i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings ( see electrical characteristics ). (2) when the mcu is in halt/active-halt mode, p a1 is automatically configured in input weak pull up and cannot be used for waking up the device. in this mode, the output state of p a1 is not driven. it is recommended to use p a1 only in input mode if halt/active-halt is used in the application. (3) in the open-drain output column, "t" defines a true open-drain i/o (p-buf fer and protection diode to v dd are not implemented) stm8s103f tssop20 pinout 5.2 figure 4: stm8s103f tssop20-pin pinout docid15441 rev 4 22 / 104 stm8s103k3 stm8s103f3 stm8s103f2 pinout and pin description
stm8s103f ufqfpn20 pinout 5.3 figure 5: stm8s103f ufqfpn20-pin pinout stm8s103f tssop20/ufqfpn20 pin description 5.4 t able 6: stm8s103f pin description alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin no. pp od speed high sink (1) ext. interr . wpu floating ufqfpn20 tsspop20 t imer 2 - channel port d4 x x o3 hs x x x i/o pd4/ beep/ 18 1 1/beep tim2_ output/ uar t1 clock ch1/ uar t1 _ck 23 / 104 docid15441 rev 4 pinout and pin description stm8s103k3 stm8s103f3 stm8s103f2 2 1 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 vcap v ss oscout/p a2 oscin/p a1 [spi_nss] tim2_ch3/(hs) p a3 nrst pd4 (hs)/beep / tim2_ch1/u ar t1_ck pd5(hs)/ain5/u ar t1_tx pd3 (hs)/ain4/tim2_ch2/adc_etr pd2(hs)[ain3]{tim2_ch3] pc4(hs)/tim1_ch4/clk_cco [ain2] [tim1_ch2n] pc5 (hs)/spi_sck [tim2_ch1] pc6(hs)/spi_mosi [tim1_ch1] pc7(hs)/spi_miso[tim1_ch2] pd1(hs)/swim [tim1_bkin] i 2 c_sd a/(t)pb5 1 0 [tim1_ch1n] [tli] tim1_ch3 /(hs)pc3 pd6(hs)/ain6/u ar t1_rx 20 v dd [adc_etr] i 2 c_scl/(t)pb4
alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin no. pp od speed high sink (1) ext. interr . wpu floating ufqfpn20 tsspop20 analog input 5/ uar t1 data transmit port d5 x x o3 hs x x x i/o pd5/ ain5/ uar t1 _tx 19 2 analog input 6/ uar t1 data receive port d6 x x o3 hs x x x i/o pd6/ ain6/ uar t1 _rx 20 3 reset x i/o nrst 1 4 resonator/ crystal in port a1 x x o1 x x x i/o p a1/ oscin (2) 2 5 resonator/ crystal out port a2 x x o1 x x x i/o p a2/ oscout 3 6 digital ground s v ss 4 7 1.8 v regulator capacitor s vcap 5 8 digital power supply s v dd 6 9 spi master/ slave select [afr1] t imer 2 channel 3 port a3 x x o3 hs x x x i/o p a3/ tim2_ ch3 [spi_ nss] 7 10 t imer 1 - break input [afr4] i 2 c data port b5 t (3) o1 x x i/o pb5/ i 2 c_ sda [tim1_ bkin] 8 1 1 adc external trigger [afr4] i 2 c clock port b4 t (3) o1 x x i/o pb4/ i 2 c_ scl 9 12 t op level interrupt t imer 1 - channel 3 port c3 x x o3 hs x x x i/o pc3/ tim1_ch3 [tli] 10 13 [afr3] t imer [tim1_ ch1n] 1 - inverted channel 1 [afr7] analog input 2 [afr2] t imer configurable clock port c4 x x o3 hs x x x i/o pc4/ clk_cco/ 1 1 14 1 - inverted output/t imer 1 - channel 4 tim1_ ch4 [ain2] channel 2 [afr7] [tim1_ ch2n] t imer 2 - channel 1 [afr0] spi clock port c5 x x o3 hs x x x i/o pc5/ spi_sck [tim2_ ch1] 12 15 docid15441 rev 4 24 / 104 stm8s103k3 stm8s103f3 stm8s103f2 pinout and pin description
alternate function after remap [option bit] default alternate function main function (after reset) output input t ype pin name pin no. pp od speed high sink (1) ext. interr . wpu floating ufqfpn20 tsspop20 t imer 1 - channel 1 [afr0] spi master out/slave in port c6 x x o3 hs x x x i/o pc6/ spi_mosi [tim1_ ch1] 13 16 t imer 1 - channel 2 [afr0] spi master in/ slave out port c7 x x o3 hs x x x i/o pc7/ spi_miso [tim1_ ch2] 14 17 swim data interface port d1 x x o4 hs x x x i/o pd1/ swim 15 18 analog input 3 [afr2] t imer port d2 x x o3 hs x x x i/o pd2 [ain3] 16 19 2 - channel 3 [afr1] [tim2_ ch3] analog input 4/ t imer 2 - port d3 x x o3 hs x x x i/o pd3/ ain4/ 17 20 channel 2/adc external trigger tim2_ ch2/ adc_ etr (1) i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings. (2) when the mcu is in halt/active-halt mode, p a1 is automatically configured in input weak pull up and cannot be used for waking up the device. in this mode, the output state of p a1 is not driven. it is recommended to use p a1 only in input mode if halt/active-halt is used in the application. (3) in the open-drain output column, "t" defines a true open-drain i/o (p-buf fer and protection diode to v dd are not implemented). alternate function remapping 5.5 as shown in the rightmost column of the pin description table, some alternate functions can be remapped at dif ferent i/o ports by programming one of eight afr (alternate function remap) option bits. when the remapping option is active, the default alternate function is no longer available. t o use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate function remapping does not ef fect gpio capabilities of the i/o ports (see the gpio section of the family reference manual, rm0016). 25 / 104 docid15441 rev 4 pinout and pin description stm8s103k3 stm8s103f3 stm8s103f2
memory and register map 6 memory map 6.1 figure 6: memory map docid15441 rev 4 26 / 104 stm8s103k3 stm8s103f3 stm8s103f2 memory and register map 0x00 9fff flash prog r am memor y (8 kb ytes) 0x00 0000 ram 0x00 03ff (1 kb yte) ? 513 b ytes stac k ? 0x00 4000 0x00 427f 640 b ytes data eepr om reser v ed reser v ed reser v ed 0x00 4280 0x00 a000 0x02 7fff 0x00 47ff 0x00 8000 32 interr upt v ectors 0x00 807f gpio and per iph. reg. 0x00 5000 0x00 57ff 0x00 5800 0x00 7fff 0x00 480b 0x00 4fff 0x00 7eff cpu/swim/deb ug/itc registers 0x00 7f00 reser v ed reser v ed option b ytes 0x00 480a 0x00 4800 0x00 0800 0x00 3fff 0x00 8080 reser v ed unique id 0x00 4864 0x00 4865 0x00 4870 0x00 4871
register map 6.2 i/o port hardware register map 6.2.1 t able 7: i/o port hardware register map reset status register name register label block address 0x00 port a data output latch register p a_odr port a 0x00 5000 0x00 port a input pin value register p a_idr 0x00 5001 0x00 port a data direction register p a_ddr 0x00 5002 0x00 port a control register 1 p a_cr1 0x00 5003 0x00 port a control register 2 p a_cr2 0x00 5004 0x00 port b data output latch register pb_odr port b 0x00 5005 0x00 port b input pin value register pb_idr 0x00 5006 0x00 port b data direction register pb_ddr 0x00 5007 0x00 port b control register 1 pb_cr1 0x00 5008 0x00 port b control register 2 pb_cr2 0x00 5009 0x00 port c data output latch register pc_odr port c 0x00 500a 0x00 port c input pin value register pb_idr 0x00 500b 0x00 port c data direction register pc_ddr 0x00 500c 0x00 port c control register 1 pc_cr1 0x00 500d 0x00 port c control register 2 pc_cr2 0x00 500e 0x00 port d data output latch register pd_odr port d 0x00 500f 0x00 port d input pin value register pd_idr 0x00 5010 0x00 port d data direction register pd_ddr 0x00 501 1 0x02 port d control register 1 pd_cr1 0x00 5012 0x00 port d control register 2 pd_cr2 0x00 5013 0x00 port e data output latch register pe_odr port e 0x00 5014 0x00 port e input pin value register pe_idr 0x00 5015 0x00 port e data direction register pe_ddr 0x00 5016 0x00 port e control register 1 pe_cr1 0x00 5017 27 / 104 docid15441 rev 4 memory and register map stm8s103k3 stm8s103f3 stm8s103f2
reset status register name register label block address 0x00 port e control register 2 pe_cr2 port e 0x00 5018 0x00 port f data output latch register pf_odr port f 0x00 5019 0x00 port f input pin value register pf_idr 0x00 501a 0x00 port f data direction register pf_ddr 0x00 501b 0x00 port f control register 1 pf_cr1 0x00 501c 0x00 port f control register 2 pf_cr2 0x00 501d general hardware register map 6.2.2 t able 8: general hardware register map reset status register name register label block address reserved area (60 bytes) 0x00 501e to 0x00 5059 0x00 flash control register 1 flash_cr1 flash 0x00 505a 0x00 flash control register 2 flash_cr2 0x00 505b 0xff flash complementary control register 2 flash_ncr2 0x00 505c 0x00 flash protection register flash _fpr 0x00 505d 0xff flash complementary protection register flash _nfpr 0x00 505e 0x00 flash in-application programming status register flash _iapsr 0x00 505f reserved area (2 bytes) 0x00 5060 to 0x00 5061 0x00 flash program memory unprotection register flash _pukr flash 0x00 5062 reserved area (1 byte) 0x00 5063 0x00 data eeprom unprotection register flash _dukr flash 0x00 5064 reserved area (59 bytes) 0x00 5065 to 0x00 509f 0x00 external interrupt control register 1 exti_cr1 itc 0x00 50a0 0x00 external interrupt control register 2 exti_cr2 0x00 50a1 docid15441 rev 4 28 / 104 stm8s103k3 stm8s103f3 stm8s103f2 memory and register map
reset status register name register label block address reserved area (17 bytes) 0x00 50a2 to 0x00 50b2 xx reset status register rst_sr rst 0x00 50b3 reserved area (12 bytes) 0x00 50b4 to 0x00 50bf 0x01 internal clock control register clk_ickr clk 0x00 50c0 0x00 external clock control register clk_eckr 0x00 50c1 reserved area (1 byte) 0x00 50c2 0xe1 clock master status register clk_cmsr clk 0x00 50c3 0xe1 clock master switch register clk_swr 0x00 50c4 0bxxxx 0000 clock switch control register clk_swcr 0x00 50c5 0x18 clock divider register clk_ckdivr 0x00 50c6 0xff peripheral clock gating register 1 clk_pckenr1 0x00 50c7 0x00 clock security system register clk_cssr 0x00 50c8 0x00 configurable clock control register clk_ccor 0x00 50c9 0xff peripheral clock gating register 2 clk_pckenr2 0x00 50ca 0x00 can clock control register clk_canccr 0x00 50cb xx hsi clock calibration trimming register clk_hsitrimr 0x00 50cc x0 swim clock control register clk_swimccr 0x00 50cd reserved area (3 bytes) 0x00 50ce to 0x00 50d0 0x7f wwdg control register wwdg_cr wwdg 0x00 50d1 0x7f wwdr window register wwdg_wr 0x00 50d2 reserved area (13 bytes) 0x00 50d3 to 00 50df - iwdg key register iwdg_kr iwdg 0x00 50e0 0x00 iwdg prescaler register iwdg_pr 0x00 50e1 0xff iwdg reload register iwdg_rlr 0x00 50e2 reserved area (13 bytes) 0x00 50e3 to 0x00 50ef 29 / 104 docid15441 rev 4 memory and register map stm8s103k3 stm8s103f3 stm8s103f2
reset status register name register label block address 0x00 a wu control/status register 1 a wu_csr1 a wu 0x00 50f0 0x3f a wu asynchronous prescaler buf fer register a wu_apr 0x00 50f1 0x00 a wu timebase selection register a wu_tbr 0x00 50f2 0x1f beep control/status register beep_csr beep 0x00 50f3 reserved area (12 bytes) 0x00 50f4 to 0x00 50ff 0x00 spi control register 1 spi_cr1 spi 0x00 5200 0x00 spi control register 2 spi_cr2 0x00 5201 0x00 spi interrupt control register spi_icr 0x00 5202 0x02 spi status register spi_sr 0x00 5203 0x00 spi data register spi_dr 0x00 5204 0x07 spi crc polynomial register spi_crcpr 0x00 5205 0xff spi rx crc register spi_rxcrcr 0x00 5206 0xff spi tx crc register spi_txcrcr 0x00 5207 reserved area (8 bytes) 0x00 5208 to 0x00 520f 0x00 i 2 c control register 1 i2c_cr1 i 2 c 0x00 5210 0x00 i 2 c control register 2 i2c_cr2 0x00 521 1 0x00 i 2 c frequency register i2c_freqr 0x00 5212 0x00 i 2 c own address register low i2c_oarl 0x00 5213 0x00 i 2 c own address register high i2c_oarh 0x00 5214 reserved 0x00 5215 0x00 i 2 c data register i2c_dr 0x00 5216 0x00 i 2 c status register 1 i2c_sr1 0x00 5217 0x00 i 2 c status register 2 i2c_sr2 0x00 5218 0x0x i 2 c status register 3 i2c_sr3 0x00 5219 0x00 i 2 c interrupt control register i2c_itr 0x00 521a 0x00 i 2 c clock control register low i2c_ccrl 0x00 521b docid15441 rev 4 30 / 104 stm8s103k3 stm8s103f3 stm8s103f2 memory and register map
reset status register name register label block address 0x00 i 2 c clock control register high i2c_ccrh i 2 c 0x00 521c 0x02 i 2 c trise register i2c_triser 0x00 521d 0x00 i 2 c packet error checking register i2c_pecr 0x00 521e reserved area (17 bytes) 0x00 521f to 0x00 522f c0h uar t1 status register uar t1_sr uar t1 0x00 5230 xxh uar t1 data register uar t1_dr 0x00 5231 00h uar t1 baud rate register 1 uar t1_brr1 0x00 5232 00h uar t1 baud rate register 2 uar t1_brr2 0x00 5233 00h uar t1 control register 1 uar t1_cr1 0x00 5234 00h uar t1 control register 2 uar t1_cr2 0x00 5235 00h uar t1 control register 3 uar t1_cr3 0x00 5236 00h uar t1 control register 4 uar t1_cr4 0x00 5237 00h uar t1 control register 5 uar t1_cr5 0x00 5238 00h uar t1 guard time register uar t1_gtr 0x00 5239 00h uar t1 prescaler register uar t1_pscr 0x00 523a reserved area (21 bytes) 0x00 523b to 0x00 523f 0x00 tim1 control register 1 tim1_cr1 tim1 0x00 5250 0x00 tim1 control register 2 tim1_cr2 0x00 5251 0x00 tim1 slave mode control register tim1_smcr 0x00 5252 0x00 tim1 external trigger register tim1_etr 0x00 5253 0x00 tim1 interrupt enable register tim1_ier 0x00 5254 0x00 tim1 status register 1 tim1_sr1 0x00 5255 0x00 tim1 status register 2 tim1_sr2 0x00 5256 0x00 tim1 event generation register tim1_egr 0x00 5257 0x00 tim1 capture/compare mode register 1 tim1_ccmr1 0x00 5258 0x00 tim1 capture/compare mode register 2 tim1_ccmr2 0x00 5259 0x00 tim1 capture/compare mode register 3 tim1_ccmr3 0x00 525a 31 / 104 docid15441 rev 4 memory and register map stm8s103k3 stm8s103f3 stm8s103f2
reset status register name register label block address 0x00 tim1 capture/compare mode register 4 tim1_ccmr4 tim1 0x00 525b 0x00 tim1 capture/compare enable register 1 tim1_ccer1 0x00 525c 0x00 tim1 capture/compare enable register 2 tim1_ccer2 0x00 525d 0x00 tim1 counter high tim1_cntrh 0x00 525e 0x00 tim1 counter low tim1_cntrl 0x00 525f 0x00 tim1 prescaler register high tim1_pscrh 0x00 5260 0x00 tim1 prescaler register low tim1_pscrl 0x00 5261 0xff tim1 auto-reload register high tim1_arrh 0x00 5262 0xff tim1 auto-reload register low tim1_arrl 0x00 5263 0x00 tim1 repetition counter register tim1_rcr 0x00 5264 0x00 tim1 capture/compare register 1 high tim1_ccr1h 0x00 5265 0x00 tim1 capture/compare register 1 low tim1_ccr1l 0x00 5266 0x00 tim1 capture/compare register 2 high tim1_ccr2h 0x00 5267 0x00 tim1 capture/compare register 2 low tim1_ccr2l 0x00 5268 0x00 tim1 capture/compare register 3 high tim1_ccr3h 0x00 5269 0x00 tim1 capture/compare register 3 low tim1_ccr3l 0x00 526a 0x00 tim1 capture/compare register 4 high tim1_ccr4h 0x00 526b 0x00 tim1 capture/compare register 4 low tim1_ccr4l 0x00 526c 0x00 tim1 break register tim1_bkr 0x00 526d 0x00 tim1 dead-time register tim1_dtr 0x00 526e 0x00 tim1 output idle state register tim1_oisr 0x00 526f reserved area (147 bytes) 0x00 5270 to 0x00 52ff 0x00 tim2 control register 1 tim2_cr1 tim2 0x00 5300 reserved 0x00 5301 reserved 0x00 5302 0x00 tim2 interrupt enable register tim2_ier 0x00 5303 0x00 tim2 status register 1 tim2_sr1 0x00 5304 docid15441 rev 4 32 / 104 stm8s103k3 stm8s103f3 stm8s103f2 memory and register map
reset status register name register label block address 0x00 tim2 status register 2 tim2_sr2 tim2 0x00 5305 0x00 tim2 event generation register tim2_egr 0x00 5306 0x00 tim2 capture/compare mode register 1 tim2_ccmr1 0x00 5307 0x00 tim2 capture/compare mode register 2 tim2_ccmr2 0x00 5308 0x00 tim2 capture/compare mode register 3 tim2_ccmr3 0x00 5309 0x00 tim2 capture/compare enable register 1 tim2_ccer1 0x00 530a 0x00 tim2 capture/compare enable register 2 tim2_ccer2 0x00 530b 0x00 tim2 counter high tim2_cntrh 00 530c0x 0x00 tim2 counter low tim2_cntrl 0x00 530d 0x00 tim2 prescaler register tim2_pscr 0x00 530e 0xff tim2 auto-reload register high tim2_arrh 0x00 530f 0xff tim2 auto-reload register low tim2_arrl 0x00 5310 0x00 tim2 capture/compare register 1 high tim2_ccr1h 0x00 531 1 0x00 tim2 capture/compare register 1 low tim2_ccr1l 0x00 5312 0x00 tim2 capture/compare reg. 2 high tim2_ccr2h 0x00 5313 0x00 tim2 capture/compare register 2 low tim2_ccr2l 0x00 5314 0x00 tim2 capture/compare register 3 high tim2_ccr3h 0x00 5315 0x00 tim2 capture/compare register 3 low tim2_ccr3l 0x00 5316 reserved area (43 bytes) 0x00 5317 to 0x00 533f 0x00 tim4 control register 1 tim4_cr1 tim4 0x00 5340 reserved 0x00 5341 reserved 0x00 5342 0x00 tim4 interrupt enable register tim4_ier 0x00 5343 0x00 tim4 status register tim4_sr 0x00 5344 0x00 tim4 event generation register tim4_egr 0x00 5345 0x00 tim4 counter tim4_cntr 0x00 5346 0x00 tim4 prescaler register tim4_pscr 0x00 5347 33 / 104 docid15441 rev 4 memory and register map stm8s103k3 stm8s103f3 stm8s103f2
reset status register name register label block address 0xff tim4 auto-reload register tim4_arr tim4 0x00 5348 reserved area (153 bytes) 0x00 5349 to 0x00 53df 0x00 adc data buf fer registers adc _dbxr adc1 0x00 53e0 to 0x00 53f3 reserved area (12 bytes) 0x00 53f4 to 0x00 53ff 0x00 adc control/status register adc _csr adc1 0x00 5400 0x00 adc configuration register 1 adc_cr1 0x00 5401 0x00 adc configuration register 2 adc_cr2 0x00 5402 0x00 adc configuration register 3 adc_cr3 0x00 5403 0x00 adc data register high adc_drh 0x00 5404 0x00 adc data register low adc_drl 0x00 5405 0x00 adc schmitt trigger disable register high adc_tdrh 0x00 5406 0x00 adc schmitt trigger disable register low adc_tdrl 0x00 5407 0x03 adc high threshold register high adc_htrh 0x00 5408 0xff adc high threshold register low adc_htrl 0x00 5409 0x00 adc low threshold register high adc_l trh 0x00 540a 0x00 adc low threshold register low adc_l trl 0x00 540b 0x00 adc analog watchdog status register high adc_a wsrh 0x00 540c 0x00 adc analog watchdog status register low adc_a wsrl 0x00 540d 0x00 adc analog watchdog control register high adc _a wcrh 0x00 540e 0x00 adc analog watchdog control register low adc_a wcrl 0x00 540f reserved area (1008 bytes) 0x00 5410 to 0x00 57ff docid15441 rev 4 34 / 104 stm8s103k3 stm8s103f3 stm8s103f2 memory and register map
cpu/swim/debug module/interrupt controller registers 6.2.3 t able 9: cpu/swim/debug module/interrupt controller registers reset status register name register label block address 0x00 accumulator a cpu (1) 0x00 7f00 0x00 program counter extended pce 0x00 7f01 0x00 program counter high pch 0x00 7f02 0x00 program counter low pcl 0x00 7f03 0x00 x index register high xh 0x00 7f04 0x00 x index register low xl 0x00 7f05 0x00 y index register high yh 0x00 7f06 0x00 y index register low yl 0x00 7f07 0x03 stack pointer high sph 0x00 7f08 0xff stack pointer low spl 0x00 7f09 0x28 condition code register ccr 0x00 7f0a reserved area (85 bytes) 0x00 7f0b to 0x00 7f5f 0x00 global configuration register cfg_gcr cpu 0x00 7f60 0xff interrupt software priority register 1 itc_spr1 itc 0x00 7f70 0xff interrupt software priority register 2 itc_spr2 0x00 7f71 0xff interrupt software priority register 3 itc_spr3 0x00 7f72 0xff interrupt software priority register 4 itc_spr4 0x00 7f73 0xff interrupt software priority register 5 itc_spr5 0x00 7f74 0xff interrupt software priority register 6 itc_spr6 0x00 7f75 0xff interrupt software priority register 7 itc_spr7 0x00 7f76 0xff interrupt software priority register 8 itc_spr8 0x00 7f77 reserved area (2 bytes) 0x00 7f78 to 0x00 7f79 0x00 swim control status register swim_csr swim 0x00 7f80 reserved area (15 bytes) 0x00 7f81 to 0x00 7f8f 35 / 104 docid15441 rev 4 memory and register map stm8s103k3 stm8s103f3 stm8s103f2
reset status register name register label block address 0xff dm breakpoint 1 register extended byte dm_bk1re dm 0x00 7f90 0xff dm breakpoint 1 register high byte dm_bk1rh 0x00 7f91 0xff dm breakpoint 1 register low byte dm_bk1rl 0x00 7f92 0xff dm breakpoint 2 register extended byte dm_bk2re 0x00 7f93 0xff dm breakpoint 2 register high byte dm_bk2rh 0x00 7f94 0xff dm breakpoint 2 register low byte dm_bk2rl 0x00 7f95 0x00 dm debug module control register 1 dm_cr1 0x00 7f96 0x00 dm debug module control register 2 dm_cr2 0x00 7f97 0x10 dm debug module control/status register 1 dm_csr1 0x00 7f98 0x00 dm debug module control/status register 2 dm_csr2 0x00 7f99 0xff dm enable function register dm_enfctr 0x00 7f9a reserved area (5 bytes) 0x00 7f9b to 0x00 7f9f (1) accessible by debug module only docid15441 rev 4 36 / 104 stm8s103k3 stm8s103f3 stm8s103f2 memory and register map
interrupt vector mapping 7 t able 10: interrupt mapping v ector address w akeup from active-halt mode w akeup from halt mode description source block irq no. 0x00 8000 y es y es reset reset 0x00 8004 - - software interrupt trap 0x00 8008 - - external top level interrupt tli 0 0x00 800c y es - auto wake up from halt a wu 1 0x00 8010 - - clock controller clk 2 0x00 8014 y es (1) y es (1) port a external interrupts exti0 3 0x00 8018 y es y es port b external interrupts exti1 4 0x00 801c y es y es port c external interrupts exti2 5 0x00 8020 y es y es port d external interrupts exti3 6 0x00 8024 y es y es port e external interrupts exti4 7 0x00 8028 - - reserved 8 0x00 802c - - reserved 9 0x00 8030 y es y es end of transfer spi 10 0x00 8034 - - tim1 update/ overflow/ underflow/ trigger/ break tim1 1 1 0x00 8038 - - tim1 capture/ compare tim1 12 0x00 803c - - tim2 update/ overflow tim2 13 0x00 8040 - - tim2 capture/ compare tim2 14 0x00 8044 - - reserved 15 0x00 8048 - - reserved 16 0x00 804c - - tx complete uar t1 17 0x00 8050 - - receive register da t a full uar t1 18 0x00 8054 y es y es i 2 c interrupt i 2 c 19 0x00 8058 - - reserved 20 0x00 805c - - reserved 21 0x00 8060 - - adc1 end of conversion/ analog watchdog interrupt adc1 22 37 / 104 docid15441 rev 4 interrupt vector mapping stm8s103k3 stm8s103f3 stm8s103f2
v ector address w akeup from active-halt mode w akeup from halt mode description source block irq no. 0x00 8064 - - tim4 update/ overflow tim4 23 0x00 8068 - - eop/wr_pg_dis flash 24 0x00 806c to 0x00 807c reserved (1) except p a1 docid15441 rev 4 38 / 104 stm8s103k3 stm8s103f3 stm8s103f2 interrupt vector mapping
option bytes 8 option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory . except for the rop (read-out protection) byte, each option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy . option bytes can be modified in icp mode (via swim) by accessing the eeprom address shown in the table below . option bytes can also be modified on the fly by the application in iap mode, except the rop option that can only be modified in icp mode (via swim). refer to the stm8s flash programming manual (pm0051) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. t able 1 1: option bytes factory default setting option bits option byte no. option name addr . 0 1 2 3 4 5 6 7 00h rop [7:0] opt0 read-out protection (rop) 0x4800 00h ubc [7:0] opt1 user boot code(ubc) 0x4801 ffh nubc [7:0] nopt1 0x4802 00h afr0 afr1 afr2 afr3 afr4 afr5 afr6 afr7 opt2 alternate function 0x4803 ffh nafr0 nafr1 nafr2 nafr3 nafr4 nafr5 nafr6 nafr7 nopt2 0x4804 remapping (afr) 00h wwdg _hal t wwdg _hw iwdg _hw lsi_ en hsi trim reserved opt3 miscell. option 0x4805h ffh nww g_hal t nwwdg _hw niwdg _hw nlsi_ en nhsi trim reserved nopt3 0x4806 00h prs c0 prs c1 cka wu sel ext clk reserved opt4 clock option 0x4807 ffh npr sc0 nprsc1 ncka wusel next clk reserved nopt4 0x4808 00h hsecnt [7:0] opt5 hse clock startup 0x4809 ffh nhsecnt [7:0] nopt5 0x480a t able 12: option byte description description option byte no. rop[7:0] memory readout protection (rop) opt0 0xaa: enable readout protection (write access via swim protocol) note: refer to the family reference manual (rm0016) section on flash/eeprom memory readout protection for details. 39 / 104 docid15441 rev 4 option bytes stm8s103k3 stm8s103f3 stm8s103f2
description option byte no. ubc[7:0] user boot code area opt1 0x00: no ubc, no write-protection 0x01: page 0 defined as ubc, memory write-protected 0x02: pages 0 to 1 defined as ubc, memory write-protected. page 0 and 1 contain the interrupt vectors. ... 0x7f: pages 0 to 126 defined as ubc, memory write-protected other values: pages 0 to 127 defined as ubc, memory write-protected note: refer to the family reference manual (rm0016) section on flash write protection for more details. afr[7:0] opt2 refer to following section for alternate function remapping decriptions of bits [7:2] and [1:0] respectively . hsitrim :high speed internal clock trimming register size opt3 0: 3-bit trimming supported in clk_hsitrimr register 1: 4-bit trimming supported in clk_hsitrimr register lsi_en :low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw : independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw : window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_hal t : window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active docid15441 rev 4 40 / 104 stm8s103k3 stm8s103f3 stm8s103f2 option bytes
description option byte no. extclk : external clock selection opt4 0: external crystal connected to oscin/oscout 1: external clock signal on oscin cka wusel :auto wake-up unit/clock 0: lsi clock source selected for a wu 1: hse clock with prescaler selected as clock source for for a wu prsc[1:0] a wu clock prescaler 0x: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 1 1: 4 mhz to 128 khz prescaler hsecnt[7:0] :hse crystal oscillator stabilization time opt5 0x00: 2048 hse cycles 0xb4: 128 hse cycles 0xd2: 8 hse cycles 0xe1: 0.5 hse cycles alternate function remapping bits 8.1 t able 13: stm8s103k alternate function remapping bits for 32-pin devices description (1) option byte no. afr7 alternate function remapping option 7 opt2 reserved. afr6 alternate function remapping option 6 0: afr6 remapping option inactive: default alternate function (2) . 1: port d7 alternate function = tim1_ch4. afr5 alternate function remapping option 5 0: afr5 remapping option inactive: default alternate function (2) . 1: port d0 alternate function = clk_cco. afr[4:2] alternate function remapping options 4:2 reserved. 41 / 104 docid15441 rev 4 option bytes stm8s103k3 stm8s103f3 stm8s103f2
description (1) option byte no. afr1 alternate function remapping option 1 0: afr1 remapping option inactive: default alternate functions (2) . 1: port a3 alternate function = spi_nss; port d2 alternate function = tim2_ch3. afr0 alternate function remapping option 0 reserved. (1) do not use more than one remapping option in the same port. it is forbidden to enable both afr1 and afr0. (2) refer to pinout description. t able 14: stm8s103f alternate function remapping bits for 20-pin devices description option byte no. afr7 alternate function remapping option 7 opt2 0: afr7 remapping option inactive: default alternate functions (1) . 1: port c3 alternate function = tim1_ch1n; port c4 alternate function = tim1_ch2n. afr6 alternate function remapping option 6 reserved. afr5 alternate function remapping option 5 reserved. afr4 alternate function remapping option 4 0: afr4 remapping option inactive: default alternate functions (1) . 1: port b4 alternate function = adc_etr; port b5 alternate function = tim1_bkin. afr3 alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function (1) . 1: port c3 alternate function = tli. afr2 alternate function remapping option 2 0: afr2 remapping option inactive: default alternate functions (1) . 1: port c4 alternate function = ain2; port d2 alternate function = ain3. docid15441 rev 4 42 / 104 stm8s103k3 stm8s103f3 stm8s103f2 option bytes
description option byte no. afr1 alternate function remapping option 1 (2) 0: afr1 remapping option inactive: default alternate functions (1) . 1: port a3 alternate function = spi_nss; port d2 alternate function = tim2_ch3. afr0 alternate function remapping option 0 (2) 0: afr0 remapping option inactive: default alternate functions (1) . 1: port c5 alternate function = tim2_ch1; port c6 alternate function = tim1_ch1; port c7 alternate function = tim1_ch2. (1) refer to pinout description. (2) do not use more than one remapping option in the same port. it is forbidden to enable both afr1 and afr0. 43 / 104 docid15441 rev 4 option bytes stm8s103k3 stm8s103f3 stm8s103f2
unique id 9 the devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. the 96 bits of the identifier can never be altered by the user . the unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. the unique device identifier is ideally suited: ? for use as serial numbers ? for use as security keys to increase the code security in the program memory while using and combining this unique id with software cryptograhic primitives and protocols before programming the internal memory . ? t o activate secure boot processes t able 15: unique id registers (96 bits) unique id bits content description address 0 1 2 3 4 5 6 7 u_id[7:0] x co-ordinate on the wafer 0x4865 u_id[15:8] 0x4866 u_id[23:16] y co-ordinate on the wafer 0x4867 u_id[31:24] 0x4868 u_id[39:32] w afer number 0x4869 u_id[47:40] lot number 0x486a u_id[55:48] 0x486b u_id[63:56] 0x486c u_id[71:64] 0x486d u_id[79:72] 0x486e u_id[87:80] 0x486f u_id[95:88] 0x4870 docid15441 rev 4 44 / 104 stm8s103k3 stm8s103f3 stm8s103f2 unique id
electrical characteristics 10 parameter conditions 10.1 unless otherwise specified, all voltages are referred to v ss . minimum and maximum values 10.1.1 unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = 25 c and t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). t ypical values 10.1.2 unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v . they are given only as design guidelines and are not tested. t ypical adc accuracy values are determined by characterization of a batch of samples from a standard dif fusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). t ypical curves 10.1.3 unless otherwise specified, all typical curves are given only as design guidelines and are not tested. loading capacitor 10.1.4 the loading conditions used for pin parameter measurement are shown in the following figure. figure 7: pin loading conditions 45 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2 stm8 pin 50 pf
pin input voltage 10.1.5 the input voltage measurement on a pin of the device is described in the following figure. figure 8: pin input voltage absolute maximum ratings 10.2 stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability . t able 16: v oltage characteristics unit max min ratings symbol v 6.5 -0.3 supply voltage (1) v ddx - v ss 6.5 v ss - 0.3 input voltage on true open drain pins (2) v in v dd + 0.3 v ss - 0.3 input voltage on any other pin (2) mv 50 v ariations between dif ferent power pins |v ddx - v dd | 50 v ariations between all the dif ferent ground pins |v ssx - v ss | see "absolute maximum ratings (electrical sensitivity)" electrostatic discharge voltage v esd (1) all power (v dd ) and ground (v ss ) pins must always be connected to the external power supply (2) i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in t able 17: current characteristics unit max (1) ratings symbol ma 100 t otal current into v dd power lines (source) (2) i vdd 80 t otal current out of v ss ground lines (sink) (2) i vss 20 output current sunk by any i/o and control pin i io - 20 output current source by any i/os and control pin 4 injected current on nrst pin i inj(pin) (3) (4) 4 injected current on oscin pin 4 injected current on any other pin (5) 20 t otal injected current (sum of all i/o and control pins) (5) i inj(pin) (3) (1) data based on characterization results, not tested in production. (2) all power (v dd ) and ground (v ss ) pins must always be connected to the external supply . (3) i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in unit max min conditions parameter symbol v 5.5 2.95 standard operating voltage v dd nf 3300 470 0.05 esr 0.2 at 1 mhz vcap external capacitor (1) c ext mw 330 lqfp32 power dissipation at t a = 85 c for suf fix 6 p d (2) 550 ufqfpn32 227 tssop20 220 ufqfpn20 83 lqfp32 power dissipation at t a = 125 c for suf fix 3 1 10 ufqfpn32 59 tssop20 55 ufqfpn20 c 85 -40 maximum power dissipation ambient temperature for 6 suf fix version t a 125 -40 maximum power dissipation ambient temperature for 3 suf fix version t a 105 -40 6 suf fix version junction temperature range t j 130 (3) -40 3 suf fix version (1) care should be taken when selecting the capacitor , due to its tolerance, as well as its dependency on temperature, dc bias and frequency in addition to other factors (2) t o calculate p dmax (t a ), use the formula p dmax jmax - t a )/ ja (see thermal characteristics ) with the value for t jmax given in operating conditions and the value for ja given in thermal characteristics . (3) jmax is given by the test limit. above this value the product behavior is not guaranteed. docid15441 rev 4 48 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
figure 9: f cpumax versus v dd t able 20: operating conditions at power-up/power-down unit max t yp min conditions parameter symbol s/v 2 v dd rise time rate t vdd 2 v dd fall time rate (1) ms 1.7 v dd rising reset release delay t temp v 2.85 2.7 2.6 power-on reset threshold v it+ 2.8 2.65 2.5 brown-out reset threshold v it- mv 70 brown-out reset hysteresis v hys(bor) (1) reset is always generated after a t temp delay . the application must ensure that v dd is still above the minimum ooperating voltage (v dd min) when the t temp delay has elapsed. vcap external capacitor 10.3.1 stabilization for the main regulator is achieved connecting an external capacitor c ext to the v cap pin. c ext is specified in the operating conditions section. care should be taken to limit the series inductance to less than 15 nh. 49 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2 16 12 8 4 0 2.95 4.0 5.0 5.5 f cpu (mhz) functionality guar anteed @t a -40 to 125 c supply v oltage functionality not guar anteed in this area
figure 10: external capacitor c ext 1. esr is the equivalent series resistance and esl is the equivalent inductance. supply current characteristics 10.3.2 the current consumption is measured as described in pin input voltage . t otal current consumption in run mode 10.3.2.1 the mcu is placed under the following conditions: ? all i/o pins in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned. subject to general operating conditions for v dd and t a . t able 21: t otal current consumption with code execution in run mode at v dd = 5 v unit max (1) t yp conditions parameter symbol ma 2.3 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code executed from ram i dd(run) 2.35 2 hse user ext. clock (16 mhz) 2 1.7 hsi rc osc. (16 mhz) 0.86 hse user ext. clock (16 mhz) f cpu = f master / 128 = 125 khz 0.87 0.7 hsi rc osc. (16 mhz) 0.58 0.46 hsi rc osc. (16 mhz/8) f cpu = f master / 128 = 15.625 khz 0.55 0.41 lsi rc osc. (128 khz) f cpu = f master = 128 khz 4.5 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code executed from flash 4.75 4.3 hse user ext. clock (16 mhz) 4.5 3.7 hsi rc osc. (16 mhz) docid15441 rev 4 50 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics esr rleak esl c
unit max (1) t yp conditions parameter symbol ma 1.05 0.84 hsi rc osc. (16 mhz/8) (2) f cpu = f master = 2 mhz supply current in run mode, code executed from flash i dd(run) 0.9 0.72 hsi rc osc. (16 mhz) f cpu = f master / 128 = 125 khz 0.58 0.46 hsi rc osc. (16 mhz/8) f cpu = f master / 128 = 15.625 khz 0.57 0.42 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals of f. t able 22: t otal current consumption with code execution in run mode at v dd = 3.3 v unit max (1) t yp conditions parameter symbol ma 1.8 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code executed from ram i dd(run) 2.3 2 hse user ext. clock (16 mhz) 2 1.5 hsi rc osc. (16 mhz) 0.81 hse user ext. clock (16 mhz) f cpu = f master / 128 = 125 khz 0.87 0.7 hsi rc osc. (16 mhz) 0.58 0.46 hsi rc osc. (16 mhz/8) f cpu = f master / 128 = 15.625 khz 0.55 0.41 lsi rc osc. (128 khz) f cpu = f master = 128 khz 4 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code executed from flash 4.7 3.9 hse user ext. clock (16 mhz) 4.5 3.7 hsi rc osc. (16 mhz) 1.05 0.84 hsi rc osc. (16 mhz/8) (2) f cpu = f master = 2 mhz 0.9 0.72 hsi rc osc. (16 mhz) f cpu = f master / 128 = 125 khz 0.58 0.46 hsi rc osc. (16 mhz/8) f cpu = f master / 128 = 15.625 khz 0.57 0.42 lsi rc osc. (128 khz) f cpu = f master = 128 khz 51 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
(1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals of f. t otal current consumption in wait mode 10.3.2.2 t able 23: t otal current consumption in wait mode at v dd = 5 v unit max (1) t yp conditions parameter symbol ma 1.6 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in wait mode i dd(wfi) 1.3 1.1 hse user ext. clock (16 mhz) 1.1 0.89 hsi rc osc. (16 mhz) 0.88 0.7 hsi rc osc. (16 mhz) f cpu = f master / 128 = 125 khz 0.57 0.45 hsi rc osc. (16 mhz/8) (2) f cpu = f master / 128 = 15.625 khz 0.54 0.4 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals of f. t able 24: t otal current consumption in wait mode at v dd = 3.3 v unit max (1) t yp conditions parameter symbol ma 1.1 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in wait mode i dd(wfi) 1.3 1.1 hse user ext. clock (16 mhz) 1.1 0.89 hsi rc osc. (16 mhz) 0.88 0.7 hsi rc osc. (16 mhz) f cpu = f master / 128 = 125 khz 0.57 0.45 hsi rc osc. (16 mhz/8) (2) f cpu = f master / 128 = 15.625 khz 0.54 0.4 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals of f. docid15441 rev 4 52 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
t otal current consumption in active halt mode 10.3.2.3 t able 25: t otal current consumption in active halt mode at v dd = 5 v unit max at 125 c (1) max at 85 c (1) t yp conditions parameter symbol clock source flash mode (3) main voltage regulator (mvr) (2) a 1030 hse crystal operating mode on supply current in active halt mode i dd(ah) osc. (16 mhz) 300 260 200 lsi rc osc. (128 khz) operating mode on supply current in active halt mode i dd(ah) 970 hse crystal power-down mode on supply current in active halt mode i dd(ah) osc. (16 mhz) 230 200 150 lsi rc osc. (128 khz) power-down mode on supply current in active halt mode i dd(ah) 1 10 85 66 lsi rc osc. (128 khz) operating mode of f supply current in active halt mode i dd(ah) 40 20 10 lsi rc osc. (128 khz) power-down mode supply current in active halt mode i dd(ah) (1) data based on characterization results, not tested in production (2) configured by the regah bit in the clk_ickr register . (3) configured by the ahal t bit in the flash_cr1 register . t able 26: t otal current consumption in active halt mode at v dd = 3.3 v unit max at 125 c (1) max at 85 c (1) t yp conditions parameter symbol clock source flash mode (3) main voltage regulator (mvr) (2) a 550 hse crystal osc. (16 mhz) operating mode on supply current in active halt mode i dd(ah) 53 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
unit max at 125 c (1) max at 85 c (1) t yp conditions parameter symbol clock source flash mode (3) main voltage regulator (mvr) (2) a 290 260 200 lsi rc osc. (128 khz) operating mode on supply current in active halt mode i dd(ah) 970 hse crystal osc. (16 mhz) power-down mode i dd(ah) 230 200 150 lsi rc osc. (128 khz) supply current in active halt mode i dd(ah) 105 80 66 lsi rc osc. (128 khz) operating mode of f i dd(ah) 35 18 10 power-down mode i dd(ah) (1) data based on characterization results, not tested in production (2) configured by the regah bit in the clk_ickr register . (3) configured by the ahal t bit in the flash_cr1 register . t otal current consumption in halt mode 10.3.2.4 t able 27: t otal current consumption in halt mode at v dd = 5 v unit max at 125 c (1) max at 85 c (1) t yp conditions parameter symbol a 105 75 63 flash in operating mode, hsi clock after wakeup supply current in halt mode i dd(h) 55 15 6.0 flash in power-down mode, hsi clock after wakeup (1) data based on characterization results, not tested in production t able 28: t otal current consumption in halt mode at v dd = 3.3 v unit max at 125 c (1) max at 85 c (1) t yp conditions parameter symbol a 100 75 60 flash in operating mode, hsi clock after wakeup supply current in halt mode i dd(h) 30 12 4.5 flash in power-down mode, hsi clock after wakeup docid15441 rev 4 54 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
(1) data based on characterization results, not tested in production low power mode wakeup times 10.3.2.5 t able 29: w akeup times unit max (1) t yp conditions parameter symbol s see note (2) w akeup time from wait mode to run mode (3) t wu(wfi) 0.56 f cpu = f master = 16 mhz. 2 (6) 1 (6) hsi (after wakeup) flash in operating mode (5) mvr voltage regulator on (4) w akeup time active halt mode to run mode (3) t wu(ah) 3 (6) hsi (after wakeup) flash in power-down mode (5) mvr voltage regulator on (4) w akeup time active halt mode to run mode (3) 48 (6) hsi (after wakeup) flash in operating mode (5) mvr voltage regulator of f (4) w akeup time active halt mode to run mode (3) 50 (6) hsi (after wakeup) flash in power-down mode (5) mvr voltage regulator of f (4) w akeup time active halt mode to run mode (3) 52 flash in operating mode (5) w akeup time from halt mode to run mode (3) t wu(h) 54 flash in power-down mode (5) (1) data guaranteed by design, not tested in production. (2) t wu(wfi) = 2 x 1/f master + 6 x 1/f cpu. (3) measured from interrupt event to interrupt vector fetch. (4) configured by the regah bit in the clk_ickr register . (5) configured by the ahal t bit in the flash_cr1 register . (6) plus 1 lsi clock depending on synchronization. 55 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
t otal current consumption and timing in forced reset state 10.3.2.6 t able 30: t otal current consumption and timing in forced reset state unit max (1) t yp conditions parameter symbol a 400 v dd = 5 v supply current in reset state (2) i dd(r) 300 v dd = 3.3 v s 150 reset pin release to vector fetch t resetbl (1) data guaranteed by design, not tested in production. (2) characterized with all i/os tied to v ss . current consumption of on-chip peripherals 10.3.2.7 subject to general operating conditions for v dd and t a . hsi internal rc/f cpu = f master = 16 mhz, v dd = 5 v t able 31: peripheral current consumption unit t yp. parameter symbol a 210 tim1 supply current (1) i dd(tim1) 130 tim2 supply current (1) i dd(tim2) 50 tim4 timer supply current (1) i dd(tim4) 120 uar t1 supply current (2) i dd(uar t1) 45 spi supply current (2) i dd(spi) 65 i 2 c supply current (2) i dd(i 2 c) 1000 adc1 supply current when converting (3) i dd(adc1) (1) data based on a dif ferential i dd measurement between reset configuration and timer counter running at 16 mhz. no ic/oc programmed (no i/o pads toggling). not tested in production. (2) data based on a dif ferential i dd measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. no i/o pads toggling. not tested in production. (3) data based on a dif ferential i dd measurement between reset configuration and continuous a/d conversions. not tested in production. docid15441 rev 4 56 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
current consumption curves 10.3.2.8 the following figures show typical current consumption measured with code executing in ram. figure 1 1: t yp i dd(run) vs. v dd hse user external clock, f cpu = 16 mhz figure 12: t yp i dd(run) vs. f cpu hse user external clock, v dd = 5 v 57 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
figure 13: t yp i dd(run) vs. v dd hsi rc osc, f cpu = 16 mhz figure 14: t yp i dd(wfi) vs. v dd hse user external clock, f cpu = 16 mhz docid15441 rev 4 58 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
figure 15: t yp i dd(wfi) vs. f cpu hse user external clock, v dd = 5 v figure 16: t yp i dd(wfi) vs. v dd hsi rc osc, f cpu = 16 mhz external clock sources and timing characteristics 10.3.3 hse user external clock subject to general operating conditions for v dd and t a . t able 32: hse user external clock characteristics unit max min conditions parameter symbol mhz 16 0 user external clock source frequency f hse_ext v v dd + 0.3 v 0.7 x v dd oscin input pin high level voltage v hseh (1) 0.3 x v dd v ss oscin input pin low level voltage v hsel (1) a +1 -1 v ss < v in < v dd oscin input leakage current i leak_hse 59 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
(1) data based on characterization results, not tested in production. figure 17: hse external clocksource hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mhz crystal/ceramic resonator oscillator . all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to the crystal resonator manufacturer for more details (frequency , package, accuracy ...). t able 33: hse oscillator characteristics unit max t yp min conditions parameter symbol mhz 16 1 external high speed oscillator frequency f hse k? 220 feedback resistor r f pf 20 recommended load capacitance (2) c (1) ma 6 (startup) c = 20 pf , hse oscillator power consumption i dd(hse) 1.6 (stabilized) (3) f osc = 16 mhz 6 (startup) c = 10 pf , 1.2 (stabilized) (3) f osc =16 mhz ma/v 5 oscillator transconductance g m ms 1 v dd is stabilized startup time t su(hse) (4) (1) c is approximately equivalent to 2 x crystal cload. docid15441 rev 4 60 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics v hseh v hsel exter nal cloc k source oscin f hse stm8
(2) the oscillator selection can be optimized in terms of supply current using a high quality resonator with small r m value. refer to crystal manufacturer for more details (3) data based on characterization results, not tested in production. (4) t su(hse) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer . figure 18: hse oscillator circuit diagram hse oscillator critical g m equation g mcrit = (2 f hse ) 2 r m (2co + c) 2 r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (see crystal specification) co: shunt capacitance (see crystal specification) c l1 = c l2 = c: grounded external capacitance g m >> g mcrit internal clock sources and timing characteristics 10.3.4 subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) t able 34: hsi oscillator characteristics unit max t yp min conditions parameter symbol mhz 16 frequency f hsi % 1 (4) user-trimmed with clk_hsitrimr register for accuracy of hsi oscillator acc hsi 61 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2 oscout oscin f hse to core c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator
unit max t yp min conditions parameter symbol given v dd and t a conditions (1) 1.3 (3) -2.5 (3) v dd = 5 v , t a = 25c (2) accuracy of hsi oscillator (factory calibrated) 2 (3) -2.5 (3) v dd = 5 v , 25 c t a 85 c 3 (2) (3) -4.5 (2) (3) 2.95 v dd 5.5 v ,-40 c t a 125 c s 1 (4) hsi oscillator wakeup time t su(hsi) including calibration a 250 (2) 170 hsi oscillator power consumption i dd(hsi) (1) refer to application note. (2) data based on characterization results, not tested in production (3) subject to further characterization to give better results (4) guaranteed by design, not tested in production. figure 19: t ypical hsi accuracy at v dd = 5 v vs 5 temperatures docid15441 rev 4 62 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
figure 20: t ypical hsi frequency variation vs v dd @ 4 temperatures low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . t able 35: lsi oscillator characteristics unit max t yp min parameter symbol khz 150 128 1 10 frequency f lsi s 7 lsi oscillator wake-up time t su(lsi) a 5 lsi oscillator power consumption i dd(lsi) figure 21: t ypical lsi frequency variation vs v dd @ 4 temperatures 63 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
memory characteristics 10.3.5 ram and hardware registers t able 36: ram and hardware registers unit min conditions parameter symbol v v it-max (2) halt mode (or reset) data retention mode (1) v rm (1) minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by design, not tested in production. (2) refer to the operating conditions section for the value of v it-max flash program memory/data eeprom memory t able 37: flash program memory/data eeprom memory unit max t yp min (1) conditions parameter symbol v 5.5 2.95 f cpu 16 mhz operating voltage (all modes, execution/write/erase) v dd ms 6.6 6 standard programming time (including erase) t prog for byte/word/block (1 byte/4 bytes/64 bytes) 3.33 3 fast programming time for 1 block (64 bytes) 3.33 3 erase time for 1 block (64 bytes) t erase cycles 10 k t a = +85 c erase/write cycles (2) (program memory) n r w 1 m 300 k t a = +125 c erase/write cycles (data memory) (2) years 20 t ret = 55c data retention (program and data memory) after t ret 10k erase/write cycles at t a = +55 c 1 t ret = 85c data retention (data memory) after 300k erase/write cyclesat t a = +125 c ma 2 supply current (flash programming or erasing for 1 to 128 bytes) i dd docid15441 rev 4 64 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
(1) data based on characterization results, not tested in production. (2) the physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. i/o port pin characteristics 10.3.6 general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor . t able 38: i/o static characteristics unit max t yp min conditions parameter symbol v 0.3 x v dd -0.3 v v dd = 5 v input low level voltage v il v dd + 0.3 v 0.7 x v dd input high level voltage v ih mv 700 hysteresis (1) v hys k 60 45 30 v dd = 5 v , v in = v ss pull-up resistor r pu ns 20 (2) fast i/os load = 50 pf rise and fall time (10 % - 90 %) t r , t f 125 (2) standard and high sink i/os load = 50 pf a 1 (2) v ss v in v dd digital input leakage current i lkg na 250 (2) v ss v in v dd analog input leakage current i lkg ana a 1 (2) injection current 4 ma leakage current in adjacent i/o i lkg(inj) (1) hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested in production. (2) data based on characterisation results, not tested in production. 65 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
figure 22: t ypical v il and v ih vs v dd @ 4 temperatures figure 23: t ypical pull-up resistance vs v dd @ 4 temperatures docid15441 rev 4 66 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
figure 24: t ypical pull-up current vs v dd @ 4 temperatures t able 39: output driving current (standard ports) unit max min conditions parameter symbol v 2 i io = 10 ma, v dd = 5 v output low level with 8 pins sunk v ol 1 (1) i io = 4 ma, v dd = 3.3 v output low level with 4 pins sunk 2.8 i io = 10 ma, v dd = 5 v output high level with 8 pins sourced v oh 2.1 (1) i io = 4 ma, v dd = 3.3 v output high level with 4 pins sourced (1) data based on characterization results, not tested in production t able 40: output driving current (true open drain ports) unit max conditions parameter symbol v 1 i io = 10 ma, v dd = 5 v output low level with 2 pins sunk v ol 1.5 (1) i io = 10 ma, v dd = 3.3 v output low level with 2 pins sunk v ol 2 (1) i io = 20 ma, v dd = 5 v output low level with 2 pins sunk v ol (1) data based on characterization results, not tested in production t able 41: output driving current (high sink ports) unit max min conditions parameter symbol v 0.8 i io = 10 ma, v dd = 5 v output low level with 8 pins sunk v ol 67 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
unit max min conditions parameter symbol v 1 (1) i io = 10 ma, v dd = 3.3 v output low level with 4 pins sunk v ol 1.5 (1) i io = 20 ma, v dd = 5 v output low level with 4 pins sunk 4.0 i io = 10 ma, v dd = 5 v output high level with 8 pins sourced v oh 2.1 (1) i io = 10 ma, v dd = 3.3 v output high level with 4 pins sourced 3.3 (1) i io = 20 ma, v dd = 5 v output high level with 4 pins sourced (1) data based on characterization results, not tested in production figure 25: t yp. v ol @ v dd = 5 v (standard ports) docid15441 rev 4 68 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
figure 26: t yp. v ol @ v dd = 3.3 v (standard ports) figure 27: t yp. v ol @ v dd = 5 v (true open drain ports) 69 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
figure 28: t yp. v ol @ v dd = 3.3 v (true open drain ports) figure 29: t yp. v ol @ v dd = 5 v (high sink ports) docid15441 rev 4 70 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
figure 30: t yp. v ol @ v dd = 3.3 v (high sink ports) figure 31: t yp. v dd - v oh @ v dd = 5 v (standard ports) 71 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
figure 32: t yp. v dd - v oh @ v dd = 3.3 v (standard ports) figure 33: t yp. v dd - v oh @ v dd = 5 v (high sink ports) docid15441 rev 4 72 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
figure 34: t yp. v dd - v oh @ v dd = 3.3 v (high sink ports) reset pin characteristics 10.3.7 subject to general operating conditions for v dd and t a unless otherwise specified. t able 42: nrst pin characteristics unit max t yp min conditions parameter symbol v 0.3 x v dd -0.3 v nrst input low level voltage (1) v il(nrst) v dd + 0.3 0.7 x v dd i ol =2 ma nrst input high level voltage (1) v ih(nrst) 0.5 nrst output low level voltage (1) v ol(nrst) k 60 40 30 nrst pull-up resistor (2) r pu(nrst) ns 75 nrst input filtered pulse (3) t i fp(nrst) 500 nrst input not filtered pulse (3) t in fp(nrst) s 20 nrst output pulse (3) t op(nrst) (1) data based on characterization results, not tested in production. (2) the r pu pull-up equivalent resistor is based on a resistive transistor (3) data guaranteed by design, not tested in production. 73 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
figure 35: t ypical nrst v il and v ih vs v dd @ 4 temperatures figure 36: t ypical nrst pull-up resistance vs v dd @ 4 temperatures docid15441 rev 4 74 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
figure 37: t ypical nrst pull-up current vs v dd @ 4 temperatures the reset network shown inthe following figure protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il max. level specified in the i/o port pin characteristics section. otherwise the reset is not taken into account internally . figure 38: recommended reset pin protection spi serial peripheral interface 10.3.8 unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). 75 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2 exter nal reset circuit (optional) 0.01 f nrst vdd rpu filter inter nal reset stm8
t able 43: spi characteristics unit max min conditions (1) parameter symbol mhz 8 0 master mode spi clock frequency f sck 1/ t c(sck) 7 (2) 0 slave mode ns 25 capacitive load: c = 30 pf spi clock rise and fall time t r(sck) t f(sck) 4 x t master slave mode nss setup time t su(nss) (3) 70 slave mode nss hold time t h(nss) (3) t sck /2 +15 t sck /2 - 15 master mode sck high and low time t w(sckh) (3) t w(sckl) (3) 5 master mode data input setup time t su(mi) (3) t su(si) (3) 5 slave mode 7 master mode data input hold time t h(mi) (3) t h(si) (3) 10 slave mode 3 x t master slave mode data output access time t a(so) (3) (4) 25 slave mode data output disable time t dis(so) (3) (5) 65 (2) slave mode (after enable edge) data output valid time t v(so) (3) 30 master mode (after enable edge) data output valid time t v(mo) (3) 27 (2) slave mode (after enable edge) data output hold time t h(so) (3) 1 1 (2) master mode (after enable edge) data output hold time t h(mo) (3) (1) parameters are given by selecting 10 mhz i/o output frequency . (2) data characterization in progress. (3) v alues based on design simulation and/or characterization results, and not tested in production. (4) min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. docid15441 rev 4 76 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
(5) min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. figure 39: spi timing diagram - slave mode and cpha = 0 figure 40: spi timing diagram - slave mode and cpha = 1 1. measurement points are made at cmos levels: 0.3vdd and 0.7 vdd. 77 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2 ai14134 sck input c p h a = 0 m o s i i n p u t m i s o o u t p u t c p h a = 0 m s b o u t m s b i n b i t 6 o u t l s b i n l s b o u t c p o l = 0 c p o l = 1 b i t 1 i n n s s input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input c p h a =1 m o s i i n p u t m i s o o u t p u t c p h a =1 m s b o u t m s b i n b i t 6 o u t l s b i n l s b o u t c p o l = 0 c p o l = 1 b i t 1 i n t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
figure 41: spi timing diagram - master mode (1) 1. measurement points are made at cmos levels: 0.3vdd and 0.7 vdd. i 2 c interface characteristics 10.3.9 t able 44: i 2 c characteristics unit fast mode i 2 c (1) standard mode i 2 c parameter symbol max (2) min (2) max (2) min (2) s 1.3 4.7 scl clock low time t w(scll) 0.6 4.0 scl clock high time t w(sclh) ns 100 250 sda setup time t su(sda) 900 (3) 0 (4) 0 (3) sda data hold time t h(sda) 300 1000 sda and scl rise time t r(sda) t r(scl) 300 300 sda and scl fall time t f(sda) t f(scl) s 0.6 4.0 st ar t condition hold time t h(st a) 0.6 4.7 repeated st ar t condition setup time t su(st a) 0.6 4.0 st op condition setup time t su(st o) docid15441 rev 4 78 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics ai14136 sck input c p h a = 0 m o s i out u t m i s o in p u t c p h a = 0 m s bin m s b out b i t 6 in l s b out l s b in c p o l = 0 c p o l = 1 b i t 1 out n s s input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input c p h a =1 c p h a =1 c p o l = 0 c p o l = 1 t su(mi) t v(mo) t h(mo)
unit fast mode i 2 c (1) standard mode i 2 c parameter symbol max (2) min (2) max (2) min (2) s 1.3 4.7 st op to st ar t condition time (bus free) t w(st o:st a) pf 400 400 capacitive load for each bus line c b (1) f master , must be at least 8 mhz to achieve max fast i 2 c speed (400khz) (2) data based on standard i 2 c protocol requirement, not tested in production (3) the maximum hold time of the start condition has only to be met if the interface does not stretch the low time (4) the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl 10-bit adc characteristics 10.3.10 subject to general operating conditions for v dd , f master , and t a unless otherwise specified. t able 45: adc characteristics unit max t yp min conditions parameter symbol mhz 4 1 v dd = 2.95 to 5.5 v adc clock frequency f adc 6 1 v dd = 4.5 to 5.5 v v v dd v ss conversion voltage range (1) v ain pf 3 internal sample and hold capacitor c adc s 0.75 f adc = 4 mhz minimum sampling time t s (1) 0.5 f adc = 6 mhz s 7 w ake-up time from standby t st ab s 3.5 f adc = 4 mhz minimum total conversion time (including sampling time, 10-bit resolution) t conv s 2.33 f adc = 6 mhz 1/f adc 14 (1) during the sample time the input capacitance c ain (3 pf max) can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no ef fect on the conversion result. v alues for the sample clock t s depend on programming. 79 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
t able 46: adc accuracy with r ain < 10 k , v dd = 5 v unit max (1) t yp conditions parameter symbol lsb 3.5 1.6 f adc = 2 mhz t otal unadjusted error (2) |e t | 4 2.2 f adc = 4 mhz 4.5 2.4 f adc = 6 mhz 2.5 1.1 f adc = 2 mhz of fset error (2) |e o | 3 1.5 f adc = 4 mhz 3 1.8 f adc = 6 mhz 3 1.5 f adc = 2 mhz gain error (2) |e g | 3 2.1 f adc = 4 mhz 4 2.2 f adc = 6 mhz 1.5 0.7 f adc = 2 mhz dif ferential linearity error (2) |e d | 1.5 0.7 f adc = 4 mhz 1.5 0.7 f adc = 6 mhz 1.5 0.6 f adc = 2 mhz integral linearity error (2) |e l | 2 0.8 f adc = 4 mhz 2 0.8 f adc = 6 mhz (1) data characterization in progress. (2) adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in the i/o port pin characteristics section does not af fect the adc accuracy . t able 47: adc accuracy with r ain < 10 k r ain , v dd = 3.3 v unit max (1) t yp conditions parameter symbol lsb 3.5 1.6 f adc = 2 mhz t otal unadjusted error (2) |e t | 4 1.9 f adc = 4 mhz 2.5 1 f adc = 2 mhz of fset error (2) |e o | 2.5 1.5 f adc = 4 mhz 3 1.3 f adc = 2 mhz gain error (2) |e g | docid15441 rev 4 80 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
unit max (1) t yp conditions parameter symbol lsb 3 2 f adc = 4 mhz gain error (2) |e g | 1 0.7 f adc = 2 mhz dif ferential linearity error (2) |e d | 1.5 0.7 f adc = 4 mhz 1.5 0.6 f adc = 2 mhz integral linearity error (2) |e l | 2 0.8 f adc = 4 mhz (1) data characterization in progress. (2) adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in i/o port pin characteristics does not af fect the adc accuracy . figure 42: adc accuracy characteristics 1. example of an actual transfer curve. 2. the ideal transfer curve 3. end point correlation line e t = t otal unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o = of fset error: deviation between the first actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = dif ferential linearity error: maximum deviation between actual steps and the ideal one. 81 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
e l = integral linearity error: maximum deviation between any actual transition and the end point correlation line. figure 43: t ypical application with adc emc characteristics 10.3.1 1 susceptibility tests are performed on a sample basis during product characterization. functional ems (electromagnetic susceptibility) 10.3.1 1.1 while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). ? fesd: functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000-4-2 standard. ? ftb: a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor , until a functional disturbance occurs. this test conforms with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709 (emc design guide for stmicrocontrollers). designing hardened software to avoid noise problems 10.3.1 1.2 emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular . therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nrst pin or the oscillator pins for 1 second. t o complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened docid15441 rev 4 82 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics ainx stm8 v dd i l 1 a v t 0.6v v t 0.6v c adc v ain r ain 10-bit a/d con v ersion c ain
to prevent unrecoverable errors occurring. see application note an1015 (software techniques for improving microcontroller emc performance). t able 48: ems data level/ class conditions parameter symbol 2/b (1) v dd = 3.3 v , t a = 25 c, f master = 16 mhz (hsi clock), conforming to iec 61000-4-2 v oltage limits to be applied on any i/o pin to induce a functional disturbance v fesd 4/a (1) v dd = 3.3 v , t a = 25 c ,f master = 16 mhz (hsi clock),conforming to iec 61000-4-4 fast transient voltage burst limits to be applied through 100 pf on v dd v eftb and v ss pins to induce a functional disturbance (1) data obtained with hsi clock configuration, after applying hw recommendations described in an2860 (emc guidelines for stm8s microcontrollers). electromagnetic interference (emi) 10.3.1 1.3 based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae iec 61967-2 which specifies the board and the loading of each pin. t able 49: emi data unit conditions parameter symbol max f hse /f cpu (1) monitored frequency band general conditions 16 mhz/16 mhz 16 mhz/8 mhz dbv 5 5 0.1 mhz to 30 mhz v dd = 5 v t a = 25 c peak level s emi 5 4 30 mhz to 130 mhz lqfp32 package 5 5 130 mhz to 1 ghz conforming to sae iec 61967-2 2.5 2.5 sae emi level sae emi level (1) data based on characterisation results, not tested in production. 83 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
absolute maximum ratings (electrical sensitivity) 10.3.1 1.4 based on three dif ferent tests (esd, dlu and lu) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity . for more details, refer to the application note an1 181. electrostatic discharge (esd) 10.3.1 1.5 electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). one model can be simulated: human body model. this test conforms to the jesd22-a1 14a/a1 15a standard. for more details, refer to the application note an1 181. t able 50: esd absolute maximum ratings unit maximum value (1) class conditions ratings symbol v 4000 a t a = 25c, conforming to jesd22-a1 14 electrostatic discharge voltage (human body model) v esd(hbm) 1000 iv t a lqfp32 package = 25c, conforming to sd22-c101 electrostatic discharge voltage (charge device model) v esd(cdm) (1) data based on characterization results, not tested in production static latch-up 10.3.1 1.6 t wo complementary static tests are required on 10 parts to assess the latch-up performance: ? a supply overvoltage (applied to each power supply pin) ? a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1 181. t able 51: electrical sensitivities class (1) conditions parameter symbol a t a = 25 c static latch-up class lu a t a = 85 c a t a = 125 c docid15441 rev 4 84 / 104 stm8s103k3 stm8s103f3 stm8s103f2 electrical characteristics
(1) class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 85 / 104 docid15441 rev 4 electrical characteristics stm8s103k3 stm8s103f3 stm8s103f2
package characteristics 1 1 ecopack packages 1 1.1 t o meet environmental requirements, st of fers these devices in dif ferent grades of ecop ack ? packages, depending on their level of environmental compliance. ecop ack ? specifications, grade definitions and product status are available at www .st.com . ecop ack ? is an st trademark. package mechanical data 1 1.2 32- pin lqfp package mechanical data 1 1.2.1 figure 44: 32-pin low profile quad flat package (7 x 7) t able 52: 32-pin low profile quad flat package mechanical data inches (1) mm dim. max t yp min max t yp min 0.0630 1.600 a 0.0059 0.0020 0.150 0.050 a1 0.0571 0.0551 0.0531 1.450 1.400 1.350 a2 0.0177 0.0146 0.01 18 0.450 0.370 0.300 b 0.0079 0.0035 0.200 0.090 c 0.3622 0.3543 0.3465 9.200 9.000 8.800 d 0.2835 0.2756 0.2677 7.200 7.000 6.800 d1 docid15441 rev 4 86 / 104 stm8s103k3 stm8s103f3 stm8s103f2 package characteristics 5v_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 16 17 24 25 b 32 1 pin 1 identification 8 9
inches (1) mm dim. max t yp min max t yp min 0.2205 5.600 d3 0.3622 0.3543 0.3465 9.200 9.000 8.800 e 0.2835 0.2756 0.2677 7.200 7.000 6.800 e1 0.2205 5.600 e3 0.0315 0.800 e 0.0295 0.0236 0.0177 0.750 0.600 0.450 l 0.0394 1.000 l1 7.0 3.5 0.0 7.0 3.5 0.0 k 0.0039 0.100 ccc (1) v alues in inches are converted from mm and rounded to 4 decimal digits 32-lead ufqfpn package mechanical data 1 1.2.2 figure 45: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) 1. the exposed pad must be soldered to the pcb. it is recommended to connect it to vss. 87 / 104 docid15441 rev 4 package characteristics stm8s103k3 stm8s103f3 stm8s103f2 a ob8_me
t able 53: 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data inches (1) mm dim. max t yp min max t yp min 0.0236 0.0217 0.0197 0.600 0.550 0.500 a 0.0020 0.0008 0.050 0.020 0 a1 0.0079 0.200 a3 0.01 18 0.0098 0.0071 0.300 0.250 0.180 b 0.2028 0.1969 0.1909 5.150 5.000 4.850 d 0.1457 0.1260 3.700 3.450 3.200 d2 0.2028 0.1969 0.1909 5.150 5.000 4.850 e 0.1457 0.1358 0.1260 3.700 3.450 3.200 e2 0.0197 0.500 e 0.0197 0.0157 0.01 18 0.500 0.400 0.300 l 0.0031 0.080 ddd (1) v alues in inches are converted from mm and rounded to 4 decimal digits. 20-lead ufqfpn package mechanical data 1 1.2.3 figure 46: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) 1. drawing is not to scale docid15441 rev 4 88 / 104 stm8s103k3 stm8s103f3 stm8s103f2 package characteristics 103_a0a5_me 11 15 16 20 1 5 d e b e e a1 a ddd l2 10 l1 a3 l3 l4
t able 54: 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data inches (1) mm dim. max t yp min max t yp min 0.1 181 3.000 d 0.1 181 3.000 e 0.0236 0.0217 0.0197 0.600 0.550 0.500 a 0.0020 0.0008 0.0000 0.050 0.020 0.000 a1 0.0060 0.152 a3 0.0197 0.500 e 0.0236 0.0217 0.0197 0.600 0.550 0.500 l1 0.0157 0.0138 0.01 18 0.400 0.350 0.300 l2 0.0059 0.150 l3 0.0079 0.200 l4 0.01 18 0.0098 0.0071 0.300 0.250 0.180 b 0.0020 0.050 ddd (1) v alues in inches are converted from mm and rounded to 4 decimal digits. 89 / 104 docid15441 rev 4 package characteristics stm8s103k3 stm8s103f3 stm8s103f2
ufqfpn recommended footprint 1 1.2.4 figure 47: recommended footprint for on-board emulation 1. drawing is not to scale docid15441 rev 4 90 / 104 stm8s103k3 stm8s103f3 stm8s103f2 package characteristics b o t t o m v i e w 4 m m [ 0 . 1 5 7 " ] 4 m m [ 0 . 1 5 7 " ] 0 . 5 m m 0 . 5 m m 0 . 3 m m [ 0 . 0 1 2 " ] 0 . 9 m m [ 0 . 0 3 5 " ] 0 . 8 m m [ 0 . 0 3 2 " ] 1 . 6 5 m m [ 0 . 0 6 5 " ] ai15319
figure 48: recommended footprint without on-board emulation 1. drawing is not to scale 2. dimensions are in millimeters 20-pin tssop package mechanical data 1 1.2.5 figure 49: 20-pin, 4.40 mm body , 0.65 mm pitch 91 / 104 docid15441 rev 4 package characteristics stm8s103k3 stm8s103f3 stm8s103f2 y a_me 1 20 cp c l e e1 d a2 a k e b 10 11 a1 l1 aaa
t able 55: 20-pin, 4.40 mm body , 0.65 mm pitch mechanical data inches (1) mm dim. max t yp min max t yp min 0.0472 1.200 a 0.0059 0.0020 0.150 0.050 a1 0.0413 0.0394 0.0315 1.050 1.000 0.800 a2 0.01 18 0.0075 0.300 0.190 b 0.0079 0.0035 0.200 0.090 c 0.2598 0.2559 0.2520 6.600 6.500 6.400 d 0.2598 0.2520 0.2441 6.600 6.400 6.200 e 0.1772 0.1732 0.1693 4.500 4.400 4.300 e1 0.0256 0.650 e 0.0295 0.0236 0.0177 0.750 0.600 0.450 l 0.0394 1.000 l1 8.0 0.0 8.0 0.0 k 0.0039 0.100 aaa (1) v alues in inches are converted from mm and rounded to 4 decimal digits thermal characteristics 1 1.3 the maximum chip junction temperature (t j max ) must never exceed the values given in operating conditions . the maximum chip-junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: ? t amax is the maximum ambient temperature in c ? ja is the package junction-to-ambient thermal resistance in c/w ? p dmax is the sum of p intmax and p i/omax (pdmax = p intmax + p i/omax ) ? p intmax is the product of i dd andv dd , expressed in w atts. this is the maximum chip internal power . ? p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh )*i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. docid15441 rev 4 92 / 104 stm8s103k3 stm8s103f3 stm8s103f2 package characteristics
t able 56: thermal characteristics unit v alue parameter (1) symbol c/w 60 thermal resistance junction-ambient (lqfp32 - 7 x 7 mm) ja c/w 22 thermal resistance junction-ambient (ufqfpn32 - 5 x 5 mm) ja3 c/w 84 thermal resistance junction-ambient (tssop20 - 4.4 mm) ja c/w 90 thermal resistance junction-ambient (ufqfpn20 - 3 x 3 mm) ja (1) thermal resistances are based on jedec jesd51-2 with 4-layer pcb in a natural convection environment. reference document 1 1.3.1 jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). a vailable from www .jedec.org. selecting the product temperature range 1 1.3.2 when ordering the microcontroller , the temperature range is specified in the order code. the following example shows how to calculate the temperature range needed for a given application. assuming the following application conditions: ? maximum ambient temperature t amax = 75 c (measured according to jesd51-2) ? i ddmax = 8 ma, v dd = 5 v ? maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 8 ma x 5 v = 400 mw p iomax = 20 x 8 ma x 0.4 v = 64 mw this gives: p intmax = 400 mw and p iomax 64 mw : p dmax = 400 mw + 64 mw thus: p dmax = 464 mw t jmax for lqfp32 can be calculated as follows, using the thermal resistance ja : t jmax = 75 c + (60 c/w x 464 mw) = 75 c + 27.8 c = 102.8 c this is within the range of the suf fix 6 version parts (-40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suf fix 6. 93 / 104 docid15441 rev 4 package characteristics stm8s103k3 stm8s103f3 stm8s103f2
ordering information 12 figure 50: stm8s103x access line ordering information scheme 1. the package pitch digit is used only when several dimensions are available for the same package. 2. a dedicated ordring information scheme will be released if, in the future, memory programming service (fastrom) is required the letter "p" will be added after stm8s. three unique letters identifying the customer application code will also be visible in the codification. example: stm8sp103k3mactr. for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www .st.com or contact the st sales of fice nearest to you. docid15441 rev 4 94 / 104 stm8s103k3 stm8s103f3 stm8s103f2 ordering information product class pin count k = 32 pins f = 20 pins p ac kage type p = tssop t = lqfp u = ufqfpn example: sub-f amily type 10x = access line 103 sub-f amily f amily type s = standard t emper ature r ange 3 = -40 c to 125 c 6 = -40 c to 85 c prog r am memor y siz e 3 = 8 kb ytes 2 = 4 kb ytes p ac king no char acter = t r a y or tube tr = t ape and reel p ac kage pitch (1) blank = 0.5 mm b = 0.65 mm c = 0.8 mm stm8 s 103 k 3 t 6 c tr stm8 microcontroller
stm8s103 f astrom microcontroller option list 12.1 (last update: sept 2009) ........................................................................................................... customer ........................................................................................................... address ........................................................................................................... contact ........................................................................................................... phone no. f astrom code name is assigned by stmicroelectronics reference f astrom code preferable format for programing code is .hex (.s19 is accepted) if data eeprom programing is required, a seperate file must be sent with the requested data. important : see the option byte section in the datasheet for authorized option byte combinations and a detailed explanation. do not use more than one remapping option in the same port. it is forbidden to enable both afr1 and afr0. device type/memory size/package (check only one option) 8 kbyte 4 kbyte f astrom device [ ] stm8s103k3 lqfp32 [ ] stm8s103k3 vfqfpn32 [ ] stm8s103f3 [ ] stm8s103f2 tssop20 conditioning (check only one option) [ ] t ape & reel or [ ] t ray special marking (check only one option) [ ] no [ ] y es authorized characters are letters, digits, '.', '-', '/' and spaces only . maximum character counts are: vfqfpn32: 1 line of 7 characters max: "_ _ _ _ _ _ _" lqfp32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" tssop20: 1 line of 10 characters max: "_ _ _ _ _ _ _ _ _ _" t emperature range [ ] -40c to +85c or [ ] -40c to +125c padding value for unused program memory (check only one option) fixed value [ ]0xff 95 / 104 docid15441 rev 4 ordering information stm8s103k3 stm8s103f3 stm8s103f2
trap instruction opcode [ ]0x83 illegal opcode (causes a reset when executed) [ ]0x75 opt0 memory readout protection (check only one option) [ ] disable or [ ] enable opt1 user boot code area (ubc) 0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below . [ ] 0: reset ubc, bit0 [ ] 1: set [ ] 0: reset ubc bit1 [ ] 1: set [ ] 0: reset ubc bit2 [ ] 1: set [ ] 0: reset ubc bit3 [ ] 1: set [ ] 0: reset ubc bit4 [ ] 1: set [ ] 0: reset ubc bit5 [ ] 1: set [ ] 0: reset ubc bit6 [ ] 1: set [ ] 0: reset ubc bit7 [ ] 1: set opt2 alternate function remapping for stm8s103k do not use more than one remapping option in the same port. it is forbidden to enable both afr1 and afr0. reserved afr0 [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description afr1 (check only one option) docid15441 rev 4 96 / 104 stm8s103k3 stm8s103f3 stm8s103f2 ordering information
[ ] 1: port a3 alternate function = spi_nss and port d2 alternate function = tim2_ch3 reserved afr2 reserved afr3 reserved afr4 [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description afr5 (check only one option) [ ] 1: port d0 alternate function = clk_cco [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description afr6 (check only one option) [ ] 1: port d7 alternate function = tim1_ch4 reserved afr7 opt2 alternate function remapping for stm8s103f do not use more than one remapping option in the same port. it is forbidden to enable both afr1 and afr0. [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description afr0 (check only one option) [ ] 1: port c5 alternate function = tim2_ch1, port c6 alternate function = tim1_ch1, and port c7 alternate function = tim1_ch2 [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description afr1 (check only one option) [ ] 1: port a3 alternate function = spi_nss and port d2 alternate function = tim2_ch3 [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description afr2 (check only one option) [ ] 1: port c4 alternate function = ain2 and port d2 alternate function = ain3 [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description afr3 (check only one option) [ ] 1: port c3 alternate function = tli [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description afr4 (check only one option) [ ] 1: port b4 alternate function = adc_etr and port b5 alternate function = tim1_bkin 97 / 104 docid15441 rev 4 ordering information stm8s103k3 stm8s103f3 stm8s103f2
reserved afr5 reserved afr6 [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description afr7 (check only one option) [ ] 1: port c3 alternate function = tim1_ch1n and port c4 alternate function = tim1_ch2n opt3 watchdog [ ] 0: no reset generated on halt if wwdg active wwdg_hal t (check only one option) [ ] 1: reset generated on halt if wwdg active [ ] 0: wwdg activated by software wwdg_hw (check only one option) [ ] 1: wwdg activated by hardware [ ] 0: iwdg activated by software iwdg_hw (check only one option) [ ] 1: iwdg activated by hardware [ ] 0: lsi clock is not available as cpu clock source lsi_en (check only one option) [ ] 1: lsi clock is available as cpu clock source [ ] 0: 3-bit trimming supported in clk_hsitrimr register hsitrim (check only one option) [ ] 1: 4-bit trimming supported in clk_hsitrimr register opt4 wakeup [ ] for 16 mhz to 128 khz prescaler prsc (check only one option) [ ] for 8 mhz to 128 khz prescaler [ ] for 4 mhz to 128 khz prescaler [ ] lsi clock source selected for a wu cka wusel (check only one option) [ ] hse clock with prescaler selected as clock source for for a wu [ ] external crystal connected to oscin/oscout extclk (check only one option) [ ] external clock signal on oscin opt5 crystal oscillator stabilization hsecnt (check only one option) [ ] 2048 hse cycles docid15441 rev 4 98 / 104 stm8s103k3 stm8s103f3 stm8s103f2 ordering information
[ ] 128 hse cycles [ ] 8 hse cycles [ ] 0.5 hse cycles opt6 is reserved ........................................................................................................... comments: ........................................................................................................... supply operating range in the application: ........................................................................................................... notes: 99 / 104 docid15441 rev 4 ordering information stm8s103k3 stm8s103f3 stm8s103f2
stm8 development tools 13 development tools for the stm8 microcontrollers include the full-featured st ice emulation system supported by a complete software tool package including c compiler , assembler and integrated development environment with high-level language debugger . in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer . emulation and in-circuit debugging tools 13.1 the st ice emulation system of fers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-ef fectiveness. in addition, stm8 application development is supported by a low-cost in-circuit debugger/programmer . the st ice is the fourth generation of full featured emulators from stmicroelectronics. it of fers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, st ice of fers in-circuit debugging and programming of stm8 microcontrollers via the stm8 single wire interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller . for improved cost ef fectiveness, st ice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. st ice key features ? occurrence and time profiling and code coverage (new features) ? advanced breakpoints with up to 4 levels of conditions ? data breakpoints ? program and data trace recording up to 128 kb records ? read/write on the fly of memory during emulation ? in-circuit debugging/programming via swim protocol ? 8-bit probe analyzer ? 1 input and 2 output triggers ? power supply follower managing application voltages between 1.62 to 5.5 v ? modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements ? supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8. software tools 13.2 stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st v isual develop (stvd) ide and the st v isual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8, which are available in a free version that outputs up to 16 kbytes of code. docid15441 rev 4 100 / 104 stm8s103k3 stm8s103f3 stm8s103f2 stm8 development tools
stm8 toolset 13.2.1 stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www .st.com/mcu. this package includes: st v isual develop C full-featured integrated development environment from st , featuring ? seamless integration of c and asm toolsets ? full-featured debugger ? project management ? syntax highlighting editor ? integrated programming interface ? support of advanced emulation features for st ice such as code profiling and coverage st v isual programmer (stvp) C easy-to-use, unlimited graphical interface allowing read, write and verify of your stm8 microcontroller s flash program memory , data eeprom and option bytes. stvp also of fers project mode for saving programming configurations and automating programming sequences. c and assembly toolchains 13.2.2 control of c and assembly toolchains is seamlessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. a vailable toolchains include: ? cosmic c compiler for stm8 C a vailable in a free version that outputs up to 16 kbytes of code. for more information, see www .cosmic-software.com. ? raisonance c compiler for stm8 C a vailable in a free version that outputs up to 16 kbytes of code. for more information, see www .raisonance.com. ? stm8 assembler linker C free assembly toolchain included in the stvd toolset, which allows you to assemble and link your application source code. programming tools 13.3 during the development cycle, st ice provides in-circuit programming of the stm8 flash microcontroller on your application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8. for production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the stm8 family . 101 / 104 docid15441 rev 4 stm8 development tools stm8s103k3 stm8s103f3 stm8s103f2
revision history 14 t able 57: document revision history changes revision date initial revision 1 02-mar-2009 added t able 2: peripheral clock gating bit assignments in clk_pckenr1/2 registers . 2 10-apr-2009 updated auto wakeup counter . modified description of pb4 and pb5 (removed x in pp column) and added footnote concerning hs i/os in vfqfpn32/lqfp32 pin description and stm8s103f tssop20/ufqfpn20 pin description . removed tim3 and uar t from t able 10: interrupt mapping . updated vcap specifications in vcap external capacitor . corrected block size in t able 37: flash program memory/data eeprom memory . updated electrical characteristics . updated t able 56: thermal characteristics . document status changed from preliminary data to datasheet. 3 10-jun-2009 replaced wfqfpn20 package with ufqfpn package. replaced vfqfn with vfqfpn. added bullet point on the unique identifier to features . updated auto wakeup counter . updated wpu and pp status of pb5/12c_sda and pb4/12c_scl pins in vfqfpn32/lqfp32 pin description and stm8s103f tssop20/ufqfpn20 pin description . removed t able 7: pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices. updated figure 6: memory map . updated reset status of port d cr1 register in t able 7: i/o port hardware register map . updated alternate function remapping descriptions in t able 13: stm8s103k alternate function remapping bits for 32-pin devices and t able 14: stm8s103f alternate function remapping bits for 20-pin devices . added unique id . updated t able 19: general operating conditions . docid15441 rev 4 102 / 104 stm8s103k3 stm8s103f3 stm8s103f2 revision history
changes revision date updated name of figure 19: t ypical hsi accuracy at vdd = 5 v vs 5 temperatures . 3 10-jun-2009 updated t able 43: spi characteristics and added tbd data. added max values to t able 46: adc accuracy with rain < 10 k , vdd= 5 v and t able 47: adc accuracy with rain < 10 k rain, vdd = 3.3 v in the 10-bit adc characteristics . updated emc characteristics . replaced vfqfpn32 package with ufqfpn32 package. 4 25-nov-2009 description : updated "timer complementary outputs" in table 1 (stm8s103xx access line features) for 20-pin packages. clock controller : replaced "tim2" and "tim3" with "reserved" and "tim2" respectively in "peripheral clock gating bit assignments in clk_pckenr1/2 registers" table. t otal current consumption in halt mode : changed the maximum current consumption limit at 125 c (and v dd = 5 v) from 35 a to 55 a. i/o port pin characteristics : added footnote concerning results that are not tested in production. functional ems (electromagnetic susceptibility) : "esd" changed to "fesd" (functional); added name of an1709; replaced "iec 1000" with "iec 61000". designing hardened software to avoid noise problems : replaced "iec 1000" with "iec 61000", added title of an1015, and added footnote to ems data table. electromagnetic interference (emi) : replaced "j 1752/3" with "iec 61967-2" and updated data of the emi data table. selecting the product temperature range : changed the value of lqfp32 7x7 mm thermal resistance from 59 c/w to 60 c/w . ordering information : updated "sub-family type" and "package pitch", added footnote regarding possible future release of a dedicated ordering information scheme. added stm8s103 f astrom microcontroller option list . 103 / 104 docid15441 rev 4 revision history stm8s103k3 stm8s103f3 stm8s103f2
please read carefully information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice. all st products are sold pursuant to st s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st assumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. if any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. unless other wise set forth in sts terms and conditions of sale st disclaims any express or implied w arranty with respect t o the use and/or sale of st products including without limit a tion implied w arranties of merchant ability , fitness for a p articular purpose (and their equiv alents under the la ws of any jurisdiction), or infringement of any p a tent , copyright or other intellectual property right . unless expressl y approved in writing by an authorized st represent a tive, st products are not recommended, authorized or w arranted for use in milit ar y , air craft , sp ace, life sa ving, or life sust aining applica tions, nor in products or systems where f ailure or malfunction ma y resul t in personal injur y ,dea th, or severe property or environment al damage. st products which are not specified as "aut omotivegrade" ma y onl y be used in aut omotive applica tions a t users own risk. resale of st products with provisions dif ferent from the statements and/or technical features set forth in this document shall immediately voidany warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoever , any liability of st . st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www .st.com docid15441 rev 4 104 / 104 stm8s103k3 stm8s103f3 stm8s103f2

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